| 56 | } |
| 57 | |
| 58 | _vifT static __fi bool vifTransfer(u32 *data, int size, bool TTE) { |
| 59 | vifStruct& vifX = GetVifX; |
| 60 | |
| 61 | // irqoffset necessary to add up the right qws, or else will spin (spiderman) |
| 62 | int transferred = vifX.irqoffset.enabled ? vifX.irqoffset.value : 0; |
| 63 | |
| 64 | vifX.vifpacketsize = size; |
| 65 | vifTransferLoop<idx>(data); |
| 66 | |
| 67 | transferred += size - vifX.vifpacketsize; |
| 68 | |
| 69 | //Make this a minimum of 1 cycle so if it's the end of the packet it doesnt just fall through. |
| 70 | //Metal Saga can do this, just to be safe :) |
| 71 | if (!idx) g_vif0Cycles += std::max(1, (int)((transferred * BIAS) >> 2)); |
| 72 | else g_vif1Cycles += std::max(1, (int)((transferred * BIAS) >> 2)); |
| 73 | |
| 74 | vifX.irqoffset.value = transferred % 4; // cannot lose the offset |
| 75 | |
| 76 | if (vifX.irq && vifX.cmd == 0) { |
| 77 | VIF_LOG("Vif%d IRQ Triggering", idx); |
| 78 | //Always needs to be set to return to the correct offset if there is data left. |
| 79 | vifX.vifstalled.enabled = VifStallEnable(vifXch); |
| 80 | vifX.vifstalled.value = VIF_IRQ_STALL; |
| 81 | } |
| 82 | |
| 83 | if (!TTE) // *WARNING* - Tags CAN have interrupts! so lets just ignore the dma modifying stuffs (GT4) |
| 84 | { |
| 85 | transferred = transferred >> 2; |
| 86 | transferred = std::min((int)vifXch.qwc, transferred); |
| 87 | vifXch.madr +=(transferred << 4); |
| 88 | vifXch.qwc -= transferred; |
| 89 | |
| 90 | hwDmacSrcTadrInc(vifXch); |
| 91 | |
| 92 | vifX.irqoffset.enabled = false; |
| 93 | |
| 94 | if(!vifXch.qwc) |
| 95 | vifX.inprogress &= ~0x1; |
| 96 | else if (vifX.irqoffset.value != 0) |
| 97 | vifX.irqoffset.enabled = true; |
| 98 | } |
| 99 | else |
| 100 | { |
| 101 | if(vifX.irqoffset.value != 0){ |
| 102 | vifX.irqoffset.enabled = true; |
| 103 | }else |
| 104 | vifX.irqoffset.enabled = false; |
| 105 | } |
| 106 | |
| 107 | vifExecQueue(idx); |
| 108 | |
| 109 | return !vifX.vifstalled.enabled; |
| 110 | } |
| 111 | |
| 112 | // When TTE is set to 1, MADR and QWC are not updated as part of the transfer. |
| 113 | bool VIF0transfer(u32 *data, int size, bool TTE) { |
nothing calls this directly
no test coverage detected