| 25 | |
| 26 | int vu0branch = 0; |
| 27 | static void _vu0Exec(VURegs* VU) |
| 28 | { |
| 29 | _VURegsNum lregs; |
| 30 | _VURegsNum uregs; |
| 31 | u32* ptr; |
| 32 | |
| 33 | ptr = (u32*)&VU->Micro[VU->VI[REG_TPC].UL]; |
| 34 | VU->VI[REG_TPC].UL += 8; |
| 35 | |
| 36 | if (ptr[1] & 0x40000000) // E flag |
| 37 | { |
| 38 | VU->ebit = 2; |
| 39 | } |
| 40 | if (ptr[1] & 0x20000000 && VU == &VU0) // M flag |
| 41 | { |
| 42 | VU->flags |= VUFLAG_MFLAGSET; |
| 43 | // Console.WriteLn("fixme: M flag set"); |
| 44 | } |
| 45 | if (ptr[1] & 0x10000000) // D flag |
| 46 | { |
| 47 | if (VU0.VI[REG_FBRST].UL & 0x4) |
| 48 | { |
| 49 | VU0.VI[REG_VPU_STAT].UL |= 0x2; |
| 50 | hwIntcIrq(INTC_VU0); |
| 51 | VU->ebit = 1; |
| 52 | } |
| 53 | } |
| 54 | if (ptr[1] & 0x08000000) // T flag |
| 55 | { |
| 56 | if (VU0.VI[REG_FBRST].UL & 0x8) |
| 57 | { |
| 58 | VU0.VI[REG_VPU_STAT].UL |= 0x4; |
| 59 | hwIntcIrq(INTC_VU0); |
| 60 | VU->ebit = 1; |
| 61 | } |
| 62 | } |
| 63 | |
| 64 | VU->code = ptr[1]; |
| 65 | VU0regs_UPPER_OPCODE[VU->code & 0x3f](&uregs); |
| 66 | |
| 67 | u64 cyclesBeforeOp = VU0.cycle - 1; |
| 68 | |
| 69 | _vuTestUpperStalls(VU, &uregs); |
| 70 | |
| 71 | /* check upper flags */ |
| 72 | if (ptr[1] & 0x80000000) // I flag |
| 73 | { |
| 74 | _vuTestPipes(VU); |
| 75 | |
| 76 | if (VU->VIBackupCycles > 0) |
| 77 | VU->VIBackupCycles -= std::min((u8)(VU0.cycle - cyclesBeforeOp), VU->VIBackupCycles); |
| 78 | |
| 79 | _vu0ExecUpper(VU, ptr); |
| 80 | |
| 81 | VU->VI[REG_I].UL = ptr[0]; |
| 82 | memset(&lregs, 0, sizeof(lregs)); |
| 83 | } |
| 84 | else |
no test coverage detected