| 248 | } |
| 249 | |
| 250 | __forceinline void CheckDMAProgress(int cid) |
| 251 | { |
| 252 | V_Core& core = Cores[cid]; |
| 253 | int adma_cbit = 1 << cid; |
| 254 | |
| 255 | if (core.DMAICounter > 0 && (psxRegs.cycle - core.LastClock) > 0) |
| 256 | { |
| 257 | const u32 amt = std::min<u64>(psxRegs.cycle - core.LastClock, (u32)core.DMAICounter); |
| 258 | core.DMAICounter -= amt; |
| 259 | core.LastClock = psxRegs.cycle; |
| 260 | |
| 261 | if (!core.AdmaInProgress) |
| 262 | { |
| 263 | if (cid == 0) |
| 264 | HW_DMA4_MADR += amt / 2; |
| 265 | if (cid == 1) |
| 266 | HW_DMA7_MADR += amt / 2; |
| 267 | } |
| 268 | |
| 269 | if (core.DMAICounter > 0) |
| 270 | { |
| 271 | CounterUpdate(core.DMAICounter); |
| 272 | return; |
| 273 | } |
| 274 | |
| 275 | for (int i = 0; i < 2; i++) |
| 276 | { |
| 277 | if (has_to_call_irq_dma[i]) |
| 278 | { |
| 279 | //ConLog("* SPU2: Irq Called (%04x) at cycle %d.\n", Spdif.Info, Cycles); |
| 280 | has_to_call_irq_dma[i] = false; |
| 281 | if (!(Spdif.Info & (4 << i)) && Cores[i].IRQEnable) |
| 282 | { |
| 283 | Spdif.Info |= (4 << i); |
| 284 | spu2Irq(); |
| 285 | } |
| 286 | } |
| 287 | } |
| 288 | |
| 289 | if (((core.AutoDMACtrl & adma_cbit) != adma_cbit) && core.ReadSize) |
| 290 | { |
| 291 | if (core.IsDMARead) |
| 292 | core.FinishDMAread(); |
| 293 | else |
| 294 | core.FinishDMAwrite(); |
| 295 | } |
| 296 | |
| 297 | if (core.DMAICounter <= 0) |
| 298 | { |
| 299 | if (cid == 0) |
| 300 | { |
| 301 | HW_DMA4_MADR = HW_DMA4_TADR; |
| 302 | spu2DMA4Irq(); |
| 303 | } |
| 304 | |
| 305 | if (cid == 1) |
| 306 | { |
| 307 | HW_DMA7_MADR = HW_DMA7_TADR; |
no test coverage detected