| 386 | } |
| 387 | |
| 388 | u16 SPU2read(u32 rmem) |
| 389 | { |
| 390 | u16 ret = 0xDEAD; |
| 391 | u32 core = 0; |
| 392 | const u32 mem = rmem & 0xFFFF; |
| 393 | u32 omem = mem; |
| 394 | |
| 395 | if (mem & 0x400) |
| 396 | { |
| 397 | omem ^= 0x400; |
| 398 | core = 1; |
| 399 | } |
| 400 | |
| 401 | if (omem == 0x1f9001AC) |
| 402 | { |
| 403 | Cores[core].ActiveTSA = Cores[core].TSA; |
| 404 | for (int i = 0; i < 2; i++) |
| 405 | { |
| 406 | if (Cores[i].IRQEnable && (Cores[i].IRQA == Cores[core].ActiveTSA)) |
| 407 | { |
| 408 | SetIrqCall(i); |
| 409 | } |
| 410 | } |
| 411 | ret = Cores[core].DmaRead(); |
| 412 | } |
| 413 | else |
| 414 | { |
| 415 | TimeUpdate(psxRegs.cycle); |
| 416 | |
| 417 | if (rmem >> 16 == 0x1f80) |
| 418 | { |
| 419 | ret = Cores[0].ReadRegPS1(rmem); |
| 420 | } |
| 421 | else if (mem >= 0x800) |
| 422 | { |
| 423 | ret = spu2Ru16(mem); |
| 424 | if (SPU2::MsgToConsole()) |
| 425 | SPU2::ConLog("* SPU2: Read from reg>=0x800: %x value %x\n", mem, ret); |
| 426 | } |
| 427 | else |
| 428 | { |
| 429 | ret = *(regtable[(mem >> 1)]); |
| 430 | #ifdef PCSX2_DEVBUILD |
| 431 | //FileLog("[%10d] SPU2 read mem %x (core %d, register %x): %x\n",Cycles, mem, core, (omem & 0x7ff), ret); |
| 432 | SPU2::WriteRegLog("read", rmem, ret); |
| 433 | #endif |
| 434 | } |
| 435 | } |
| 436 | |
| 437 | return ret; |
| 438 | } |
| 439 | |
| 440 | void SPU2write(u32 rmem, u16 value) |
| 441 | { |
no test coverage detected