| 12 | static u32 mfifotransferred = 0; // FIXME: Remove next time someone bumps savestates, no longer required. |
| 13 | |
| 14 | static void TestClearVUs(u32 madr, u32 qwc, bool isWrite) |
| 15 | { |
| 16 | if (madr >= 0x11000000 && (madr < 0x11010000)) |
| 17 | { |
| 18 | // Access to VU memory is only allowed when the VU is stopped |
| 19 | // Use Psychonauts for testing |
| 20 | |
| 21 | if ((madr < 0x11008000) && (VU0.VI[REG_VPU_STAT].UL & 0x1)) |
| 22 | { |
| 23 | _vu0FinishMicro(); |
| 24 | //Catch up VU1 too |
| 25 | CpuVU1->ExecuteBlock(0); |
| 26 | } |
| 27 | if ((madr >= 0x11008000) && (VU0.VI[REG_VPU_STAT].UL & 0x100) && (!THREAD_VU1 || !isWrite)) |
| 28 | { |
| 29 | if (THREAD_VU1) |
| 30 | vu1Thread.WaitVU(); |
| 31 | else |
| 32 | CpuVU1->Execute(vu1RunCycles); |
| 33 | cpuRegs.cycle = VU1.cycle; |
| 34 | //Catch up VU0 too |
| 35 | CpuVU0->ExecuteBlock(0); |
| 36 | } |
| 37 | |
| 38 | if (madr < 0x11004000) |
| 39 | { |
| 40 | if(isWrite) |
| 41 | { |
| 42 | DbgCon.Warning("scratch pad clearing vu0"); |
| 43 | |
| 44 | CpuVU0->Clear(madr&0xfff, qwc * 16); |
| 45 | } |
| 46 | |
| 47 | if(((madr & 0xff0) + (qwc * 16)) > 0x1000 ) |
| 48 | { |
| 49 | DevCon.Warning("Warning! SPR%d Crossing in to VU0 Micro Mirror address! Start MADR = %x, End MADR = %x", isWrite ? 0 : 1, madr, madr + (qwc * 16)); |
| 50 | } |
| 51 | } |
| 52 | else if (madr >= 0x11008000 && madr < 0x1100c000) |
| 53 | { |
| 54 | if(isWrite) |
| 55 | { |
| 56 | DbgCon.Warning("scratch pad clearing vu1"); |
| 57 | |
| 58 | CpuVU1->Clear(madr&0x3fff, qwc * 16); |
| 59 | } |
| 60 | } |
| 61 | else if (madr >= 0x11004000 && madr < 0x11008000) |
| 62 | { |
| 63 | // SPR trying to write to to VU0 Mem mirror address. |
| 64 | if(((madr & 0xff0) + (qwc * 16)) > 0x1000) |
| 65 | { |
| 66 | DevCon.Warning("Warning! SPR%d Crossing in to VU0 Mem Mirror address! Start MADR = %x, End MADR = %x", isWrite ? 0 : 1, madr, madr + (qwc * 16)); |
| 67 | } |
| 68 | } |
| 69 | } |
| 70 | } |
| 71 |
no test coverage detected