| 458 | } |
| 459 | |
| 460 | __ri void cpuTestINTCInts() |
| 461 | { |
| 462 | // Check the COP0's Status register for general interrupt disables, and the 0x400 |
| 463 | // bit (which is INTC master toggle). |
| 464 | if (!cpuIntsEnabled(0x400)) |
| 465 | return; |
| 466 | |
| 467 | if ((psHu32(INTC_STAT) & psHu32(INTC_MASK)) == 0) |
| 468 | return; |
| 469 | |
| 470 | cpuSetNextEventDelta(4); |
| 471 | if (eeEventTestIsActive && (psxRegs.iopCycleEE > 0)) |
| 472 | { |
| 473 | psxRegs.iopBreak += psxRegs.iopCycleEE; // record the number of cycles the IOP didn't run. |
| 474 | psxRegs.iopCycleEE = 0; |
| 475 | } |
| 476 | } |
| 477 | |
| 478 | __fi void cpuTestDMACInts() |
| 479 | { |
no test coverage detected