| 476 | } |
| 477 | |
| 478 | __fi void cpuTestDMACInts() |
| 479 | { |
| 480 | // Check the COP0's Status register for general interrupt disables, and the 0x800 |
| 481 | // bit (which is the DMAC master toggle). |
| 482 | if (!cpuIntsEnabled(0x800)) |
| 483 | return; |
| 484 | |
| 485 | if (((psHu16(0xe012) & psHu16(0xe010)) == 0) && |
| 486 | ((psHu16(0xe010) & 0x8000) == 0)) |
| 487 | return; |
| 488 | |
| 489 | cpuSetNextEventDelta(4); |
| 490 | if (eeEventTestIsActive && (psxRegs.iopCycleEE > 0)) |
| 491 | { |
| 492 | psxRegs.iopBreak += psxRegs.iopCycleEE; // record the number of cycles the IOP didn't run. |
| 493 | psxRegs.iopCycleEE = 0; |
| 494 | } |
| 495 | } |
| 496 | |
| 497 | __fi void cpuTestTIMRInts() |
| 498 | { |
no test coverage detected