| 77 | } |
| 78 | |
| 79 | __fi uint dmacInterrupt() |
| 80 | { |
| 81 | if( ((psHu16(DMAC_STAT + 2) & psHu16(DMAC_STAT)) == 0 ) && |
| 82 | ( psHu16(DMAC_STAT) & 0x8000) == 0 ) |
| 83 | { |
| 84 | //DevCon.Warning("No valid DMAC interrupt MASK %x STAT %x", psHu16(DMAC_STAT+2), psHu16(DMAC_STAT)); |
| 85 | return 0; |
| 86 | } |
| 87 | |
| 88 | if (!dmacRegs.ctrl.DMAE || psHu8(DMAC_ENABLER+2) == 1) |
| 89 | { |
| 90 | //DevCon.Warning("DMAC Suspended or Disabled on interrupt"); |
| 91 | return 0; |
| 92 | } |
| 93 | |
| 94 | DMA_LOG("dmacInterrupt %x", |
| 95 | ((psHu16(DMAC_STAT + 2) & psHu16(DMAC_STAT)) | |
| 96 | (psHu16(DMAC_STAT) & 0x8000)) |
| 97 | ); |
| 98 | |
| 99 | //cpuException(0x800, cpuRegs.branch); |
| 100 | return 0x800; |
| 101 | } |
| 102 | |
| 103 | void hwIntcIrq(int n) |
| 104 | { |
no outgoing calls
no test coverage detected