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hub / github.com/PCSX2/pcsx2 / SpeedRead

Function SpeedRead

pcsx2/DEV9/DEV9.cpp:437–539  ·  view source on GitHub ↗

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435}
436
437u16 SpeedRead(u32 addr, int width)
438{
439 u16 hard = 0;
440 switch (addr)
441 {
442 case 0x10000020:
443 //DevCon.WriteLn("DEV9: SPD_R_20 %dbit read %x", width, 1);
444 return 1;
445 case SPD_R_INTR_STAT:
446 //DevCon.WriteLn("DEV9: SPD_R_INTR_STAT %dbit read %x", width, dev9.irqcause);
447 return dev9.irqcause;
448
449 case SPD_R_INTR_MASK:
450 //DevCon.WriteLn("DEV9: SPD_R_INTR_MASK %dbit read %x", width, dev9.irqmask);
451 return dev9.irqmask;
452
453 case SPD_R_PIO_DATA:
454
455 /*if(dev9.eeprom_dir!=1)
456 {
457 hard=0;
458 break;
459 }*/
460
461 if (dev9.eeprom_state == EEPROM_TDATA)
462 {
463 if (dev9.eeprom_command == 2) // read
464 {
465 if (dev9.eeprom_bit != 0xFF)
466 hard = ((dev9.eeprom[dev9.eeprom_address] << dev9.eeprom_bit) & 0x8000) >> 11;
467 dev9.eeprom_bit++;
468 if (dev9.eeprom_bit == 16)
469 {
470 dev9.eeprom_address++;
471 dev9.eeprom_bit = 0;
472 }
473 }
474 }
475 //DevCon.WriteLn("DEV9: SPD_R_PIO_DATA %dbit read %x", width, hard);
476 return hard;
477
478 case SPD_R_REV_1:
479 //DevCon.WriteLn("DEV9: SPD_R_REV_1 %dbit read %x", width, 0);
480 return 0;
481
482 case SPD_R_REV_2:
483 hard = 0x11;
484 //DevCon.WriteLn("DEV9: STD_R_REV_2 %dbit read %x", width, hard);
485 return hard;
486
487 case SPD_R_REV_3:
488 // The Expansion bay always says HDD and Ethernet are supported, we need to keep HDD enabled and we handle it elsewhere.
489 // Ethernet we will turn off as not sure on what that would do right now, but no known game cares if it's off.
490 if (EmuConfig.DEV9.EthEnable)
491 hard |= SPD_CAPS_SMAP;
492
493 // TODO: Do we need flash? my 50003 model doesn't report this, but it does report DVR capable aka (1<<4), was that intended?
494 hard |= SPD_CAPS_ATA | SPD_CAPS_FLASH;

Callers 2

DEV9read8Function · 0.85
DEV9read16Function · 0.85

Calls 2

WriteLnMethod · 0.45
ErrorMethod · 0.45

Tested by

no test coverage detected