| 885 | } |
| 886 | |
| 887 | static __fi void rcntWmode(int index, u32 value) |
| 888 | { |
| 889 | rcntSyncCounter(index); |
| 890 | |
| 891 | // Clear OverflowReached and TargetReached flags (0xc00 mask), but *only* if they are set to 1 in the |
| 892 | // given value. (yes, the bits are cleared when written with '1's). |
| 893 | |
| 894 | counters[index].modeval &= ~(value & 0xc00); |
| 895 | counters[index].modeval = (counters[index].modeval & 0xc00) | (value & 0x3ff); |
| 896 | EECNT_LOG("EE Counter[%d] writeMode = %x passed value=%x", index, counters[index].modeval, value); |
| 897 | |
| 898 | switch (counters[index].mode.ClockSource) { //Clock rate divisers *2, they use BUSCLK speed not PS2CLK |
| 899 | case 0: counters[index].rate = 2; break; |
| 900 | case 1: counters[index].rate = 32; break; |
| 901 | case 2: counters[index].rate = 512; break; |
| 902 | case 3: counters[index].rate = vSyncInfo.hBlank+vSyncInfo.hRender; break; |
| 903 | } |
| 904 | |
| 905 | // In case the rate has changed we need to set the start cycle to the previous tick. |
| 906 | counters[index].startCycle = cpuRegs.cycle & ~((u64)counters[index].rate - 1); |
| 907 | _rcntSetGate(index); |
| 908 | _rcntSet(index); |
| 909 | } |
| 910 | |
| 911 | static __fi void rcntWcount(int index, u32 value) |
| 912 | { |
no test coverage detected