| 632 | } |
| 633 | |
| 634 | __fi void rcntUpdate_hScanline() |
| 635 | { |
| 636 | if (!cpuTestCycle(hsyncCounter.startCycle, hsyncCounter.deltaCycles)) |
| 637 | return; |
| 638 | |
| 639 | //iopEventAction = 1; |
| 640 | if (hsyncCounter.Mode == MODE_HBLANK) |
| 641 | { //HBLANK End / HRENDER Begin |
| 642 | |
| 643 | // Setup the hRender's start and end cycle information: |
| 644 | hsyncCounter.startCycle += vSyncInfo.hBlank; // start (absolute cycle value) |
| 645 | hsyncCounter.deltaCycles = vSyncInfo.hRender; // endpoint (delta from start value) |
| 646 | if (!GSSMODE1reg.SINT) |
| 647 | { |
| 648 | rcntEndGate(false, hsyncCounter.startCycle); |
| 649 | psxHBlankEnd(); |
| 650 | } |
| 651 | |
| 652 | hsyncCounter.Mode = MODE_HRENDER; |
| 653 | } |
| 654 | else |
| 655 | { //HBLANK START / HRENDER End |
| 656 | |
| 657 | // set up the hblank's start and end cycle information: |
| 658 | hsyncCounter.startCycle += vSyncInfo.hRender; // start (absolute cycle value) |
| 659 | hsyncCounter.deltaCycles = vSyncInfo.hBlank; // endpoint (delta from start value) |
| 660 | if (!GSSMODE1reg.SINT) |
| 661 | { |
| 662 | if (!CSRreg.HSINT) |
| 663 | { |
| 664 | CSRreg.HSINT = true; |
| 665 | if (!GSIMR.HSMSK) |
| 666 | gsIrq(); |
| 667 | } |
| 668 | |
| 669 | rcntStartGate(false, hsyncCounter.startCycle); |
| 670 | psxHBlankStart(); |
| 671 | } |
| 672 | |
| 673 | hsyncCounter.Mode = MODE_HBLANK; |
| 674 | |
| 675 | #ifdef VSYNC_DEBUG |
| 676 | hsc++; |
| 677 | #endif |
| 678 | } |
| 679 | } |
| 680 | |
| 681 | static __fi void _cpuTestTarget(int i) |
| 682 | { |
no test coverage detected