Function CACHE

pcsx2/Cache.cpp:385–507

			extern int Dcache;
			void CACHE()
			{
				u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
				// CACHE_LOG("cpuRegs.GPR.r[_Rs_].UL[0] = %x, IMM = %x RT = %x", cpuRegs.GPR.r[_Rs_].UL[0], _Imm_, _Rt_);

				switch (_Rt_)
				{
					case 0x1a: //DHIN (Data Cache Hit Invalidate)
						doCacheHitOp(addr, "DHIN", [](CacheLine line) {
							line.clear();
						});
						break;

					case 0x18: //DHWBIN (Data Cache Hit WriteBack with Invalidate)
						doCacheHitOp(addr, "DHWBIN", [](CacheLine line) {
							line.writeBackIfNeeded();
							line.clear();
						});
						break;

					case 0x1c: //DHWOIN (Data Cache Hit WriteBack Without Invalidate)
						doCacheHitOp(addr, "DHWOIN", [](CacheLine line) {
							line.writeBackIfNeeded();
						});
						break;

					case 0x16: //DXIN (Data Cache Index Invalidate)
					{
						const int index = cache.setIdxFor(addr);
						const int way = addr & 0x1;
						CacheLine line = cache.lineAt(index, way);

						CACHE_LOG("CACHE DXIN addr %x, index %d, way %d, flag %x", addr, index, way, line.tag.flags());

						line.clear();
						break;
					}

					case 0x11: //DXLDT (Data Cache Load Data into TagLo)
					{
						const int index = cache.setIdxFor(addr);
						const int way = addr & 0x1;
						CacheLine line = cache.lineAt(index, way);

						cpuRegs.CP0.n.TagLo = *reinterpret_cast<u32*>(&line.data.bytes[addr & 0x3C]);

						CACHE_LOG("CACHE DXLDT addr %x, index %d, way %d, DATA %x OP %x", addr, index, way, cpuRegs.CP0.n.TagLo, cpuRegs.code);
						break;
					}

					case 0x10: //DXLTG (Data Cache Load Tag into TagLo)
					{
						const int index = (addr >> 6) & 0x3F;
						const int way = addr & 0x1;
						CacheLine line = cache.lineAt(index, way);

						// DXLTG demands that SYNC.L is called before this command, which forces the cache to write back, so presumably games are checking the cache has updated the memory
						// For speed, we will do it here.