| 352 | } |
| 353 | |
| 354 | void WriteTLB(int i) |
| 355 | { |
| 356 | tlb[i].PageMask.UL = cpuRegs.CP0.n.PageMask; |
| 357 | tlb[i].EntryHi.UL = cpuRegs.CP0.n.EntryHi; |
| 358 | tlb[i].EntryLo0.UL = cpuRegs.CP0.n.EntryLo0; |
| 359 | tlb[i].EntryLo1.UL = cpuRegs.CP0.n.EntryLo1; |
| 360 | |
| 361 | // Setting the cache mode to reserved values is vaguely defined in the manual. |
| 362 | // I found that SPR is set to cached regardless. |
| 363 | // Non-SPR entries default to uncached on reserved cache modes. |
| 364 | if (tlb[i].isSPR()) |
| 365 | { |
| 366 | tlb[i].EntryLo0.C = 3; |
| 367 | tlb[i].EntryLo1.C = 3; |
| 368 | } |
| 369 | else |
| 370 | { |
| 371 | if (!tlb[i].EntryLo0.isValidCacheMode()) |
| 372 | tlb[i].EntryLo0.C = 2; |
| 373 | if (!tlb[i].EntryLo1.isValidCacheMode()) |
| 374 | tlb[i].EntryLo1.C = 2; |
| 375 | } |
| 376 | |
| 377 | if (!tlb[i].isSPR() && ((tlb[i].EntryLo0.V && tlb[i].EntryLo0.isCached()) || (tlb[i].EntryLo1.V && tlb[i].EntryLo1.isCached()))) |
| 378 | { |
| 379 | const size_t idx = cachedTlbs.count; |
| 380 | cachedTlbs.CacheEnabled0[idx] = tlb[i].EntryLo0.isCached() ? ~0 : 0; |
| 381 | cachedTlbs.CacheEnabled1[idx] = tlb[i].EntryLo1.isCached() ? ~0 : 0; |
| 382 | cachedTlbs.PFN1s[idx] = tlb[i].PFN1(); |
| 383 | cachedTlbs.PFN0s[idx] = tlb[i].PFN0(); |
| 384 | cachedTlbs.PageMasks[idx] = ConvertPageMask(tlb[i].PageMask.UL); |
| 385 | |
| 386 | cachedTlbs.count++; |
| 387 | } |
| 388 | |
| 389 | MapTLB(tlb[i], i); |
| 390 | } |
| 391 | |
| 392 | namespace R5900 { |
| 393 | namespace Interpreter { |