| 290 | } |
| 291 | |
| 292 | void UnmapTLB(const tlbs& t, int i) |
| 293 | { |
| 294 | //Console.WriteLn("Clear TLB %d: %08x-> [%08x %08x] S=%d G=%d ASID=%d Mask= %03X", i,t.VPN2,t.PFN0,t.PFN1,t.S,t.G,t.ASID,t.Mask); |
| 295 | u32 mask, addr; |
| 296 | u32 saddr, eaddr; |
| 297 | |
| 298 | if (t.isSPR()) |
| 299 | { |
| 300 | vtlb_VMapUnmap(t.VPN2(), 0x4000); |
| 301 | return; |
| 302 | } |
| 303 | |
| 304 | if (t.EntryLo0.V) |
| 305 | { |
| 306 | mask = ((~t.Mask()) << 1) & 0xfffff; |
| 307 | saddr = t.VPN2() >> 12; |
| 308 | eaddr = saddr + t.Mask() + 1; |
| 309 | // Console.WriteLn("Clear TLB: %08x ~ %08x",saddr,eaddr-1); |
| 310 | for (addr = saddr; addr < eaddr; addr++) |
| 311 | { |
| 312 | if ((addr & mask) == ((t.VPN2() >> 12) & mask)) |
| 313 | { //match |
| 314 | memClearPageAddr(addr << 12); |
| 315 | Cpu->Clear(addr << 12, 0x400); |
| 316 | } |
| 317 | } |
| 318 | } |
| 319 | |
| 320 | if (t.EntryLo1.V) |
| 321 | { |
| 322 | mask = ((~t.Mask()) << 1) & 0xfffff; |
| 323 | saddr = (t.VPN2() >> 12) + t.Mask() + 1; |
| 324 | eaddr = saddr + t.Mask() + 1; |
| 325 | // Console.WriteLn("Clear TLB: %08x ~ %08x",saddr,eaddr-1); |
| 326 | for (addr = saddr; addr < eaddr; addr++) |
| 327 | { |
| 328 | if ((addr & mask) == ((t.VPN2() >> 12) & mask)) |
| 329 | { //match |
| 330 | memClearPageAddr(addr << 12); |
| 331 | Cpu->Clear(addr << 12, 0x400); |
| 332 | } |
| 333 | } |
| 334 | } |
| 335 | |
| 336 | for (size_t i = 0; i < cachedTlbs.count; i++) |
| 337 | { |
| 338 | if (cachedTlbs.PFN0s[i] == t.PFN0() && cachedTlbs.PFN1s[i] == t.PFN1() && cachedTlbs.PageMasks[i] == ConvertPageMask(t.PageMask.UL)) |
| 339 | { |
| 340 | for (size_t j = i; j < cachedTlbs.count - 1; j++) |
| 341 | { |
| 342 | cachedTlbs.CacheEnabled0[j] = cachedTlbs.CacheEnabled0[j + 1]; |
| 343 | cachedTlbs.CacheEnabled1[j] = cachedTlbs.CacheEnabled1[j + 1]; |
| 344 | cachedTlbs.PFN0s[j] = cachedTlbs.PFN0s[j + 1]; |
| 345 | cachedTlbs.PFN1s[j] = cachedTlbs.PFN1s[j + 1]; |
| 346 | cachedTlbs.PageMasks[j] = cachedTlbs.PageMasks[j + 1]; |
| 347 | } |
| 348 | cachedTlbs.count--; |
| 349 | break; |
no test coverage detected