| 55 | // |
| 56 | |
| 57 | static __fi bool PERF_ShouldCountEvent(uint evt) |
| 58 | { |
| 59 | switch (evt) |
| 60 | { |
| 61 | // This is a rough table of actions for various PCR modes. Some of these |
| 62 | // can be implemented more accurately later. Others (WBBs in particular) |
| 63 | // probably cannot without some severe complications. |
| 64 | |
| 65 | // left sides are PCR0 / right sides are PCR1 |
| 66 | |
| 67 | case 1: // cpu cycle counter. |
| 68 | case 2: // single/dual instruction issued |
| 69 | case 3: // Branch issued / Branch mispredicated |
| 70 | return true; |
| 71 | |
| 72 | case 4: // BTAC/TLB miss |
| 73 | case 5: // ITLB/DTLB miss |
| 74 | case 6: // Data/Instruction cache miss |
| 75 | return false; |
| 76 | |
| 77 | case 7: // Access to DTLB / WBB single request fail |
| 78 | case 8: // Non-blocking load / WBB burst request fail |
| 79 | case 9: |
| 80 | case 10: |
| 81 | return false; |
| 82 | |
| 83 | case 11: // CPU address bus busy / CPU data bus busy |
| 84 | return false; |
| 85 | |
| 86 | case 12: // Instruction completed |
| 87 | case 13: // non-delayslot instruction completed |
| 88 | case 14: // COP2/COP1 instruction complete |
| 89 | case 15: // Load/Store completed |
| 90 | return true; |
| 91 | } |
| 92 | |
| 93 | return false; |
| 94 | } |
| 95 | |
| 96 | // Diagnostics for event modes that we just ignore for now. Using these perf units could |
| 97 | // cause compat issues in some very odd/rare games, so if this msg comes up who knows, |