| 486 | } |
| 487 | |
| 488 | void MFC0() |
| 489 | { |
| 490 | // Note on _Rd_ Condition 9: CP0.Count should be updated even if _Rt_ is 0. |
| 491 | if ((_Rd_ != 9) && !_Rt_) |
| 492 | return; |
| 493 | |
| 494 | //if(bExecBIOS == FALSE && _Rd_ == 25) Console.WriteLn("MFC0 _Rd_ %x = %x", _Rd_, cpuRegs.CP0.r[_Rd_]); |
| 495 | switch (_Rd_) |
| 496 | { |
| 497 | case 12: |
| 498 | cpuRegs.GPR.r[_Rt_].SD[0] = (s32)(cpuRegs.CP0.r[_Rd_] & 0xf0c79c1f); |
| 499 | break; |
| 500 | |
| 501 | case 25: |
| 502 | if (0 == (_Imm_ & 1)) // MFPS, register value ignored |
| 503 | { |
| 504 | cpuRegs.GPR.r[_Rt_].SD[0] = (s32)cpuRegs.PERF.n.pccr.val; |
| 505 | } |
| 506 | else if (0 == (_Imm_ & 2)) // MFPC 0, only LSB of register matters |
| 507 | { |
| 508 | COP0_UpdatePCCR(); |
| 509 | cpuRegs.GPR.r[_Rt_].SD[0] = (s32)cpuRegs.PERF.n.pcr0; |
| 510 | } |
| 511 | else // MFPC 1 |
| 512 | { |
| 513 | COP0_UpdatePCCR(); |
| 514 | cpuRegs.GPR.r[_Rt_].SD[0] = (s32)cpuRegs.PERF.n.pcr1; |
| 515 | } |
| 516 | /*Console.WriteLn("MFC0 PCCR = %x PCR0 = %x PCR1 = %x IMM= %x", params |
| 517 | cpuRegs.PERF.n.pccr, cpuRegs.PERF.n.pcr0, cpuRegs.PERF.n.pcr1, _Imm_ & 0x3F);*/ |
| 518 | break; |
| 519 | |
| 520 | case 24: |
| 521 | COP0_LOG("MFC0 Breakpoint debug Registers code = %x", cpuRegs.code & 0x3FF); |
| 522 | break; |
| 523 | |
| 524 | case 9: |
| 525 | { |
| 526 | s64 incr = cpuRegs.cycle - cpuRegs.lastCOP0Cycle; |
| 527 | if (incr == 0) |
| 528 | incr++; |
| 529 | cpuRegs.CP0.n.Count += incr; |
| 530 | cpuRegs.lastCOP0Cycle = cpuRegs.cycle; |
| 531 | if (!_Rt_) |
| 532 | break; |
| 533 | } |
| 534 | [[fallthrough]]; |
| 535 | |
| 536 | default: |
| 537 | cpuRegs.GPR.r[_Rt_].SD[0] = (s32)cpuRegs.CP0.r[_Rd_]; |
| 538 | } |
| 539 | } |
| 540 | |
| 541 | void MTC0() |
| 542 | { |
nothing calls this directly
no test coverage detected