Assume pixel format is FLOAT for all channels.

marker output is also

Macro: Set the rounding mode bits of the MXCSR control and status register to the value in unsigned 32-bit integer a. The rounding mode may contain an

Add the lower single-precision (32-bit) floating-point element in a and b, store the result in the lower element of dst, and copy the upper 3 packed e

Compare packed double-precision (64-bit) floating-point elements in a and b for greater-than-or-equal, and store the results in dst. https://www.intel

Compare packed double-precision (64-bit) floating-point elements in a and b for greater-than, and store the results in dst. https://www.intel.com/cont

Compare packed double-precision (64-bit) floating-point elements in a and b for less-than-or-equal, and store the results in dst. https://www.intel.co

Compare packed signed 16-bit integers in a and b for less-than, and store the results in dst. Note: This intrinsic emits the pcmpgtw instruction with

Compare packed double-precision (64-bit) floating-point elements in a and b for less-than, and store the results in dst. https://www.intel.com/content

Compare packed double-precision (64-bit) floating-point elements in a and b for not-equal, and store the results in dst. https://www.intel.com/content

Compare packed double-precision (64-bit) floating-point elements in a and b for not-greater-than-or-equal, and store the results in dst. https://www.i

Compare packed single-precision (32-bit) floating-point elements in a and b for not-greater-than-or-equal, and store the results in dst. https://www.i

Compare packed double-precision (64-bit) floating-point elements in a and b for not-greater-than, and store the results in dst. https://www.intel.com/

Compare packed single-precision (32-bit) floating-point elements in a and b for not-greater-than, and store the results in dst. https://www.intel.com/

Compare packed double-precision (64-bit) floating-point elements in a and b for not-less-than-or-equal, and store the results in dst. https://www.inte

Compare packed double-precision (64-bit) floating-point elements in a and b for not-less-than, and store the results in dst. https://www.intel.com/con

Compare packed double-precision (64-bit) floating-point elements in a and b to see if neither is NaN, and store the results in dst. https://www.intel.

Compare packed single-precision (32-bit) floating-point elements in a and b to see if neither is NaN, and store the results in dst. https://www.intel.

Compare packed double-precision (64-bit) floating-point elements in a and b to see if either is NaN, and store the results in dst. https://www.intel.c

Compare packed single-precision (32-bit) floating-point elements in a and b to see if either is NaN, and store the results in dst. https://www.intel.c

Compare the lower double-precision (64-bit) floating-point element in a and b for equality, and return the boolean result (0 or 1). https://www.intel.

Compare the lower single-precision (32-bit) floating-point element in a and b for equality, and return the boolean result (0 or 1). https://www.intel.

Sign extend packed 16-bit integers in a to packed 32-bit integers, and store the results in dst. https://www.intel.com/content/www/us/en/docs/intrinsi

Sign extend packed 8-bit integers in a to packed 32-bit integers, and store the results in dst. https://www.intel.com/content/www/us/en/docs/intrinsic

Convert packed single-precision (32-bit) floating-point elements in a to packed 16-bit integers, and store the results in dst. Note: this intrinsic wi

Divide packed double-precision (64-bit) floating-point elements in a by packed elements in b, and store the results in dst. https://www.intel.com/cont

Load 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from memory into dst. mem_addr must be aligned on a 16-byte bou

Compare packed double-precision (64-bit) floating-point elements in a and b, and store packed maximum values in dst. https://www.intel.com/content/www

Compare packed double-precision (64-bit) floating-point elements in a and b, and store packed minimum values in dst. https://www.intel.com/content/www

Convert packed signed 16-bit integers from a and b to packed 8-bit integers using unsigned saturation, and store the results in dst. https://www.intel

Convert packed signed 32-bit integers from a and b to packed 16-bit integers using unsigned saturation, and store the results in dst. https://www.inte

Count the number of bits set to 1 in unsigned 64-bit integer a, and return that count in dst. https://www.intel.com/content/www/us/en/docs/intrinsics-

Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in a, store the result in the lower element of dst, a

Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in a, store the result in the lower eleme

Broadcast 64-bit integer a to all elements of dst. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set1_epi64x

Set packed single-precision (32-bit) floating-point elements in dst with the supplied values in reverse order. https://www.intel.com/content/www/us/en

Return vector of type __m128d with all elements set to zero. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_setzero

Compute the square root of packed double-precision (64-bit) floating-point elements in a, and store the results in dst. https://www.intel.com/content/

Subtract packed double-precision (64-bit) floating-point elements in b from packed double-precision (64-bit) floating-point elements in a, and store t

Subtract the lower single-precision (32-bit) floating-point element in b from the lower single-precision (32-bit) floating-point element in a, store t

emulate vaddvq u8 variant */

* Builds the index */