| 43 | const int default_prio = 300; |
| 44 | |
| 45 | struct AbsvalOps : public MTNodeOps |
| 46 | { |
| 47 | AbsvalOps() |
| 48 | { |
| 49 | name_ = "arm_abs_fp32"; |
| 50 | } |
| 51 | |
| 52 | bool OnBind(Node* node) |
| 53 | { |
| 54 | inplace_t io_map; |
| 55 | |
| 56 | io_map[0] = 0; |
| 57 | |
| 58 | node->SetAttr(ATTR_INPLACE, io_map); |
| 59 | return true; |
| 60 | } |
| 61 | |
| 62 | bool Prerun(Node* node) |
| 63 | { |
| 64 | return true; |
| 65 | } |
| 66 | |
| 67 | bool Run(Node* node) |
| 68 | { |
| 69 | Tensor* input_tensor = node->GetInputTensor(0); |
| 70 | const TShape& shape = input_tensor->GetShape(); |
| 71 | |
| 72 | float* data = ( float* )get_tensor_mem(input_tensor); |
| 73 | |
| 74 | int channel_num = shape.GetC(); |
| 75 | int batch_number = shape.GetN(); |
| 76 | int channel_size = shape.GetW() * shape.GetH(); |
| 77 | |
| 78 | for(int c = 0; c < channel_num * batch_number; c++) |
| 79 | { |
| 80 | for(int i = 0; i < (channel_size & -4); i += 4) |
| 81 | { |
| 82 | float32x4_t _p = vld1q_f32(data); |
| 83 | _p = vabsq_f32(_p); |
| 84 | vst1q_f32(data, _p); |
| 85 | |
| 86 | data += 4; |
| 87 | } |
| 88 | for(int i = channel_size & ~3; i < channel_size; i++) |
| 89 | { |
| 90 | if (*data < 0) |
| 91 | *data = -*data; |
| 92 | data++; |
| 93 | } |
| 94 | } |
| 95 | |
| 96 | /* |
| 97 | int elem_num = shape.GetSize(); |
| 98 | for(int i = 0; i < (elem_num & -4); i += 4) |
| 99 | { |
| 100 | float32x4_t _p = vld1q_f32(data); |
| 101 | _p = vabsq_f32(_p); |
| 102 | vst1q_f32(data, _p); |
nothing calls this directly
no outgoing calls
no test coverage detected