Method write

icicle-cortexm/src/arm.rs:43–49

(&mut self, cpu: &mut Cpu)

    }

    fn write(&mut self, cpu: &mut Cpu) {
        let xpsr = cpu.read_var::<u32>(self.xpsr) & crate::arm::XPSR_NZCV_MASK;
        cpu.write_var::<u8>(self.ng, ((xpsr >> 31) & 0b1) as u8);
        cpu.write_var::<u8>(self.zr, ((xpsr >> 30) & 0b1) as u8);
        cpu.write_var::<u8>(self.cy, ((xpsr >> 29) & 0b1) as u8);
        cpu.write_var::<u8>(self.ov, ((xpsr >> 28) & 0b1) as u8);
    }
}

/// Most of this should probably be implemented as part of the SLEIGH specification instead.