Returns a mapping from Unicorn Register IDs to Icicle varnodes. This is needed for compatability with the C code in Fuzzware.
(cpu: &Cpu)
| 280 | /// Returns a mapping from Unicorn Register IDs to Icicle varnodes. This is needed for compatability |
| 281 | /// with the C code in Fuzzware. |
| 282 | pub(crate) fn map_uc_to_varnodes(cpu: &Cpu) -> Vec<pcode::VarNode> { |
| 283 | let mut vars = vec![pcode::VarNode::NONE; UC_ARM_REG_ENDING as usize]; |
| 284 | |
| 285 | let mut map = |id: uc_arm_reg::Type, name: &str| match cpu.arch.sleigh.get_varnode(name) { |
| 286 | Some(reg) => vars[id as usize] = reg, |
| 287 | None => eprintln!("{name} not found in Sleigh spec"), |
| 288 | }; |
| 289 | |
| 290 | // map(UC_ARM_REG_APSR, "apsr"); |
| 291 | // map(UC_ARM_REG_APSR_NZCV, "apsr_nzcv"); |
| 292 | map(UC_ARM_REG_CPSR, "cpsr"); |
| 293 | map(UC_ARM_REG_FPEXC, "fpexc"); |
| 294 | // map(UC_ARM_REG_FPINST, "fpinst"); |
| 295 | map(UC_ARM_REG_FPSCR, "fpscr"); |
| 296 | // map(UC_ARM_REG_FPSCR_NZCV, "fpscr_nzcv"); |
| 297 | map(UC_ARM_REG_FPSID, "fpsid"); |
| 298 | // map(UC_ARM_REG_ITSTATE, "itstate"); |
| 299 | map(UC_ARM_REG_LR, "lr"); |
| 300 | map(UC_ARM_REG_PC, "pc"); |
| 301 | map(UC_ARM_REG_SP, "sp"); |
| 302 | map(UC_ARM_REG_SPSR, "spsr"); |
| 303 | map(UC_ARM_REG_D0, "d0"); |
| 304 | map(UC_ARM_REG_D1, "d1"); |
| 305 | map(UC_ARM_REG_D2, "d2"); |
| 306 | map(UC_ARM_REG_D3, "d3"); |
| 307 | map(UC_ARM_REG_D4, "d4"); |
| 308 | map(UC_ARM_REG_D5, "d5"); |
| 309 | map(UC_ARM_REG_D6, "d6"); |
| 310 | map(UC_ARM_REG_D7, "d7"); |
| 311 | map(UC_ARM_REG_D8, "d8"); |
| 312 | map(UC_ARM_REG_D9, "d9"); |
| 313 | map(UC_ARM_REG_D10, "d10"); |
| 314 | map(UC_ARM_REG_D11, "d11"); |
| 315 | map(UC_ARM_REG_D12, "d12"); |
| 316 | map(UC_ARM_REG_D13, "d13"); |
| 317 | map(UC_ARM_REG_D14, "d14"); |
| 318 | map(UC_ARM_REG_D15, "d15"); |
| 319 | map(UC_ARM_REG_D16, "d16"); |
| 320 | map(UC_ARM_REG_D17, "d17"); |
| 321 | map(UC_ARM_REG_D18, "d18"); |
| 322 | map(UC_ARM_REG_D19, "d19"); |
| 323 | map(UC_ARM_REG_D20, "d20"); |
| 324 | map(UC_ARM_REG_D21, "d21"); |
| 325 | map(UC_ARM_REG_D22, "d22"); |
| 326 | map(UC_ARM_REG_D23, "d23"); |
| 327 | map(UC_ARM_REG_D24, "d24"); |
| 328 | map(UC_ARM_REG_D25, "d25"); |
| 329 | map(UC_ARM_REG_D26, "d26"); |
| 330 | map(UC_ARM_REG_D27, "d27"); |
| 331 | map(UC_ARM_REG_D28, "d28"); |
| 332 | map(UC_ARM_REG_D29, "d29"); |
| 333 | map(UC_ARM_REG_D30, "d30"); |
| 334 | map(UC_ARM_REG_D31, "d31"); |
| 335 | // map(UC_ARM_REG_FPINST2, "fpinst2"); |
| 336 | map(UC_ARM_REG_MVFR0, "mvfr0"); |
| 337 | map(UC_ARM_REG_MVFR1, "mvfr1"); |
| 338 | // map(UC_ARM_REG_MVFR2, "mvfr2"); |
| 339 | map(UC_ARM_REG_Q0, "q0"); |