| 65 | #define SPI_CS_HOLD_DELAY_RES_S 16 |
| 66 | |
| 67 | void modSPIInit(modSPIConfiguration config) |
| 68 | { |
| 69 | if (NULL == gConfig) { |
| 70 | if ((13 != config->mosi_pin) || (12 != config->miso_pin) || (14 != config->clock_pin)) { |
| 71 | modLog("invalid SPI"); |
| 72 | return; |
| 73 | } |
| 74 | |
| 75 | WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105); // clear bit 9 |
| 76 | |
| 77 | PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, 2); // HSPIQ MISO |
| 78 | PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 2); // HSPID MOSI |
| 79 | PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, 2); // CLK |
| 80 | |
| 81 | gSPIDataCount = -1; |
| 82 | SET_PERI_REG_MASK(SPI_FLASH_CMD(HSPI), SPI_FLASH_USR); |
| 83 | |
| 84 | SET_PERI_REG_BITS(SPI_CTRL1(HSPI), SPI_CS_HOLD_DELAY, 0, SPI_CS_HOLD_DELAY_S); |
| 85 | |
| 86 | ETS_SPI_INTR_ATTACH(spiTxInterrupt, NULL); |
| 87 | ETS_SPI_INTR_ENABLE(); |
| 88 | } |
| 89 | |
| 90 | if (80000000 == config->hz) { |
| 91 | #define hspi_enable_80Mhz() WRITE_PERI_REG(PERIPHS_IO_MUX, 0x305) |
| 92 | hspi_enable_80Mhz(); |
| 93 | config->reserved = SPI_CLK_EQU_SYSCLK; |
| 94 | } |
| 95 | else |
| 96 | config->reserved = frequencyToSPIClock(config->hz); |
| 97 | |
| 98 | modSPISetMode(config->mode); |
| 99 | } |
| 100 | |
| 101 | void modSPIUninit(modSPIConfiguration config) |
| 102 | { |
no test coverage detected