| 357 | } |
| 358 | |
| 359 | void uart_irq() |
| 360 | { |
| 361 | Serial serial; |
| 362 | uint8_t post = 0; |
| 363 | int i; |
| 364 | |
| 365 | for (i=0; i<2; i++) { |
| 366 | serial = uart_in_use[i]; |
| 367 | if (!serial) |
| 368 | continue; |
| 369 | uart_set_irq_enables(serial->uart, false, false); |
| 370 | while (uart_is_writable(serial->uart) && (0 != fifo_length(&serial->tx_fifo))) { |
| 371 | uint8_t c; |
| 372 | if (0 == fifo_get(&serial->tx_fifo, &c)) |
| 373 | uart_write_blocking(serial->uart, &c, 1); |
| 374 | else |
| 375 | break; |
| 376 | } |
| 377 | |
| 378 | serial->txInterruptEnabled = false; |
| 379 | if (!fifo_full(&serial->tx_fifo)) { |
| 380 | if (serial->onWritable) { |
| 381 | post |= (0 == serial->isWritable); |
| 382 | serial->isWritable = 1; |
| 383 | } |
| 384 | } |
| 385 | if (0 != fifo_length(&serial->tx_fifo)) |
| 386 | serial->txInterruptEnabled = true; |
| 387 | |
| 388 | while (uart_is_readable(serial->uart) && !fifo_full(&serial->rx_fifo)) { |
| 389 | uint8_t c = uart_getc(serial->uart); |
| 390 | fifo_put(&serial->rx_fifo, c); |
| 391 | } |
| 392 | |
| 393 | if (0 == (FIFO_SIZE - fifo_length(&serial->rx_fifo))) |
| 394 | serial->rxInterruptEnabled = false; |
| 395 | else if (serial->onReadable) { |
| 396 | post |= (0 == serial->isReadable); |
| 397 | serial->isReadable = 1; |
| 398 | } |
| 399 | |
| 400 | if (post) { |
| 401 | // __atomic_add_fetch(&serial->useCount, 1, __ATOMIC_SEQ_CST); |
| 402 | serial->useCount += 1; |
| 403 | if (!serial->msgOut) { |
| 404 | serial->msgOut++; |
| 405 | modMessagePostToMachineFromISR(serial->the, serialDeliver, serial); |
| 406 | } |
| 407 | } |
| 408 | } |
| 409 | |
| 410 | for (i=0; i<2; i++) { |
| 411 | serial = uart_in_use[i]; |
| 412 | if (!serial) |
| 413 | continue; |
| 414 | uart_set_irq_enables(serial->uart, serial->rxInterruptEnabled, serial->txInterruptEnabled); |
| 415 | } |
| 416 | } |
no test coverage detected