| 150 | } |
| 151 | |
| 152 | void ResizeImpl::exec_gi( |
| 153 | _megdnn_tensor_in src, _megdnn_tensor_in dst, _megdnn_workspace workspace) { |
| 154 | bool is_contiguous = src.layout.is_contiguous() && dst.layout.is_contiguous(); |
| 155 | bool is_dtype_same = src.layout.dtype == dst.layout.dtype; |
| 156 | bool is_dtype_fp32 = src.layout.dtype == dtype::Float32(); |
| 157 | bool is_dtype_supported = is_dtype_same && is_dtype_fp32; |
| 158 | |
| 159 | bool is_nchw_fp32 = param().format == param::Resize::Format::NCHW && is_dtype_fp32; |
| 160 | bool is_nchw44_fp32 = |
| 161 | param().format == param::Resize::Format::NCHW44 && is_dtype_fp32; |
| 162 | bool is_imode_nearest = |
| 163 | param().imode == param::Resize::InterpolationMode::INTER_NEAREST; |
| 164 | bool is_imode_linear = |
| 165 | param().imode == param::Resize::InterpolationMode::INTER_LINEAR; |
| 166 | bool is_imode_supported = is_imode_nearest || is_imode_linear; |
| 167 | |
| 168 | bool is_upsample2 = src.layout.shape[2] * 2 == dst.layout.shape[2] && |
| 169 | src.layout.shape[3] * 2 == dst.layout.shape[3]; |
| 170 | bool usable = is_contiguous && is_dtype_supported && is_imode_supported; |
| 171 | |
| 172 | if (param().format == param::Resize::Format::NHWC && |
| 173 | (src.layout[3] == 1 || src.layout[3] == 3) && is_nhwc_contig_wc(src.layout) && |
| 174 | is_dtype_fp32) { |
| 175 | MEGDNN_DISPATCH_CPU_KERN_OPR(resize_cv_gi_exec(src, dst, param().imode)); |
| 176 | } else if (!usable) { |
| 177 | exec_fallback(src, dst, workspace); |
| 178 | } else if (is_dtype_fp32) { |
| 179 | auto kern_param = KernParam<float>::from_tensors( |
| 180 | param().format, param().imode, src, dst, workspace); |
| 181 | if (is_nchw44_fp32) { |
| 182 | if (is_upsample2) { |
| 183 | if (is_imode_nearest) { |
| 184 | MIDOUT_BEGIN(megdnn_fallback_resize, midout_iv(0)) { |
| 185 | MEGDNN_DISPATCH_CPU_KERN_OPR( |
| 186 | resize_nearest_upsample2_nchw44_gi_fp32(kern_param)); |
| 187 | } |
| 188 | MIDOUT_END(); |
| 189 | } else { |
| 190 | megdnn_assert(is_imode_linear, "invalid imode"); |
| 191 | MIDOUT_BEGIN(megdnn_fallback_resize, midout_iv(1)) { |
| 192 | MEGDNN_DISPATCH_CPU_KERN_OPR( |
| 193 | resize_linear_upsample2_nchw44_gi_fp32(kern_param)); |
| 194 | } |
| 195 | MIDOUT_END(); |
| 196 | } |
| 197 | } else { |
| 198 | if (is_imode_nearest) { |
| 199 | MIDOUT_BEGIN(megdnn_fallback_resize, midout_iv(2)) { |
| 200 | MEGDNN_DISPATCH_CPU_KERN_OPR( |
| 201 | resize_direct_nearest_nchw44_gi_fp32(kern_param)); |
| 202 | } |
| 203 | MIDOUT_END(); |
| 204 | } else { |
| 205 | megdnn_assert(is_imode_linear, "invalid imode"); |
| 206 | MIDOUT_BEGIN(megdnn_fallback_resize, midout_iv(3)) { |
| 207 | MEGDNN_DISPATCH_CPU_KERN_OPR( |
| 208 | resize_direct_linear_nchw44_gi_fp32(kern_param)); |
| 209 | } |
nothing calls this directly
no test coverage detected