| 54 | } // namespace intl |
| 55 | |
| 56 | void GaussianBlurImpl::exec( |
| 57 | _megdnn_tensor_in src, _megdnn_tensor_in dst, _megdnn_workspace workspace) { |
| 58 | megdnn_assert( |
| 59 | src.layout.dtype == dtype::Uint8() || src.layout.dtype == dtype::Float32()); |
| 60 | check_exec(src.layout, dst.layout, workspace.size); |
| 61 | |
| 62 | auto stream = cuda_stream(handle()); |
| 63 | //! src layout is the same as dst layout |
| 64 | size_t N = src.layout.shape[0]; |
| 65 | size_t batch_size = 0; |
| 66 | #define cb(DType) \ |
| 67 | if (src.layout.dtype == DType()) { \ |
| 68 | using ctype = typename DTypeTrait<DType>::ctype; \ |
| 69 | ctype* src_ptr = src.ptr<ctype>() + curr_batch * src.layout.stride[0]; \ |
| 70 | ctype* dst_ptr = dst.ptr<ctype>() + curr_batch * src.layout.stride[0]; \ |
| 71 | batch_size = std::min<size_t>(N - curr_batch, max_batch_x_channel); \ |
| 72 | intl::gaussian_blur_exec<ctype>( \ |
| 73 | src_ptr, dst_ptr, batch_size, src.layout.shape[1], \ |
| 74 | src.layout.shape[2], src.layout.shape[3], src.layout.stride[0], \ |
| 75 | src.layout.stride[1], src.layout.stride[2], src.layout.stride[3], \ |
| 76 | workspace.ptr<uint8_t>(), m_kernel_height, m_kernel_width, m_sigma_x, \ |
| 77 | m_sigma_y, param().border_mode, stream); \ |
| 78 | } |
| 79 | |
| 80 | size_t max_batch_x_channel = max_batch_x_channel_size(); |
| 81 | size_t curr_batch = 0; |
| 82 | if (N <= max_batch_x_channel) { |
| 83 | cb(dtype::Uint8); |
| 84 | cb(dtype::Float32); |
| 85 | } else { |
| 86 | while (curr_batch < N) { |
| 87 | cb(dtype::Uint8); |
| 88 | cb(dtype::Float32); |
| 89 | |
| 90 | curr_batch += max_batch_x_channel; |
| 91 | } |
| 92 | } |
| 93 | #undef cb |
| 94 | } |
| 95 | |
| 96 | } // namespace cuda |
| 97 | } // namespace megdnn |
nothing calls this directly
no test coverage detected