Function TEST_F

dnn/test/cuda/group_conv.cpp:13–66

namespace test {

TEST_F(CUDA, GROUP_CONV_FORWARD) {
    bool is_int_available = check_compute_capability(6, 1);
    auto run = [&](size_t N, size_t IC, size_t IH, size_t IW, size_t FH, size_t FW,
                   size_t OC, size_t /* OH */, size_t /* OW */, size_t PH, size_t PW,
                   size_t SH, size_t SW, size_t DH, size_t DW, size_t group) {
        {
            // float case
            Checker<Convolution> checker(handle_cuda());
            Convolution::Param param;
            param.sparse = Convolution::Param::Sparse::GROUP;
            param.pad_h = PH;
            param.pad_w = PW;
            param.stride_h = SH;
            param.stride_w = SW;
            param.dilate_h = DH;
            param.dilate_w = DW;
            auto ICg = IC / group;
            auto OCg = OC / group;
            checker.set_param(param).exec(
                    {{N, IC, IH, IW}, {group, OCg, ICg, FH, FW}, {}});
        }
        if (is_int_available) {
            // int 8x8x32 case
            Checker<Convolution> checker(handle_cuda());
            Convolution::Param param;
            param.sparse = Convolution::Param::Sparse::GROUP;
            param.format = Convolution::Param::Format::NHWC;
            param.pad_h = PH;
            param.pad_w = PW;
            param.stride_h = SH;
            param.stride_w = SW;
            param.dilate_h = DH;
            param.dilate_w = DW;
            auto ICg = IC / group;
            auto OCg = OC / group;
            UniformIntRNG rng(-4, 4);
            checker.set_param(param)
                    .set_dtype(0, dtype::Int8())
                    .set_dtype(1, dtype::Int8())
                    .set_dtype(2, dtype::Int32())
                    .set_rng(0, &rng)
                    .set_rng(1, &rng)
                    .exec({{N, IH, IW, IC}, {group, OCg, FH, FW, ICg}, {}});
        }
    };
    // normal case
    run(2, 64, 7, 7, 3, 3, 32, 5, 5, 0, 0, 1, 1, 1, 1, 2);
    // padded case
    run(2, 32, 7, 7, 3, 3, 64, 7, 7, 1, 1, 1, 1, 1, 1, 4);
    // strided case
    run(2, 32, 7, 7, 3, 3, 64, 3, 3, 0, 0, 2, 2, 1, 1, 8);
    // dilated case
    run(2, 32, 7, 7, 3, 3, 64, 3, 3, 0, 0, 1, 1, 2, 2, 8);
}

TEST_F(CUDA, GROUP_CONV_FORWARD_1x1) {
    auto run = [&](size_t N, size_t IC, size_t IH, size_t IW, size_t FH, size_t FW,