| 665 | } |
| 666 | } else if (param().mode == Param::Mode::NCHW_NCHW64) { |
| 667 | MIDOUT_BEGIN( |
| 668 | megdnn_naive_relayout_format, midout_iv(Param::Mode::NCHW_NCHW64)) { |
| 669 | size_t c = src.layout[1]; |
| 670 | if (c % 64 != 0) { |
| 671 | uint8_t zp = 0; |
| 672 | if (src.layout.dtype.enumv() == DTypeEnum::Quantized4Asymm) { |
| 673 | zp = src.layout.dtype.param<dtype::Quantized4Asymm>().zero_point; |
| 674 | zp = (zp & 0xf) | (zp << 4); |
| 675 | } |
| 676 | MEGDNN_DISPATCH_CPU_KERN( |
| 677 | m_handle, memset(workspace.raw_ptr, zp, |
| 678 | exec_workspace_layout.span().dist_byte())); |
| 679 | TensorND ws_nd(workspace.raw_ptr, exec_workspace_layout); |
| 680 | MEGDNN_DISPATCH_CPU_KERN(m_handle, padding_to_workspace(ws_nd, src);); |
| 681 | exec_src_nd = TensorND{workspace.raw_ptr, exec_src_nd.layout}; |
| 682 | } |
| 683 | } |
| 684 | MIDOUT_END(); |
| 685 | } else if (param().mode == Param::Mode::NCHW_NCHW4_IC_SMALL_CONV_DENSE_WEIGHT) { |
| 686 | cb(1, 4, NCHW_NCHW4_IC_SMALL_CONV_DENSE_WEIGHT); |
no test coverage detected