| 626 | } |
| 627 | |
| 628 | void resize_linear_8u_neon(const Mat8u& src, Mat8u& dst) { |
| 629 | AlignedVector<int> tabsx(dst.rows()); |
| 630 | AlignedVector<int> tabsy(dst.cols()); |
| 631 | AlignedVector<int> tabrx(dst.rows()); |
| 632 | AlignedVector<int> tabry(dst.cols()); |
| 633 | build_tabs_linear_8u(src, dst, tabsx, tabsy, tabrx, tabry); |
| 634 | |
| 635 | if (src.channels() == 1) { |
| 636 | AlignedVector<int> cache0(dst.cols()), cache1(dst.cols()); |
| 637 | int dstrows = dst.rows(); |
| 638 | int dstcols = dst.cols(); |
| 639 | for (int dx = 0; dx < dstrows; ++dx) { |
| 640 | if (dx == 0 || tabsx[dx] != tabsx[dx - 1]) { |
| 641 | if (dx > 0 && tabsx[dx] == tabsx[dx - 1] + 1) { |
| 642 | calc_cache_8uc1_1( |
| 643 | src, dst, tabsx, tabsy, tabrx, tabry, dx, cache0, cache1); |
| 644 | } else { |
| 645 | calc_cache_8uc1_2( |
| 646 | src, dst, tabsx, tabsy, tabrx, tabry, dx, cache0, cache1); |
| 647 | } |
| 648 | } |
| 649 | int rx = tabrx[dx]; |
| 650 | int irx = (1 << SCALE) - rx; |
| 651 | uchar* pdst = dst.ptr(dx); |
| 652 | int dy = 0; |
| 653 | |
| 654 | const int* cache0_ptr = cache0.data(); |
| 655 | const int* cache1_ptr = cache1.data(); |
| 656 | int32x4_t v_rx = vdupq_n_s32(rx); |
| 657 | int32x4_t v_irx = vdupq_n_s32(irx); |
| 658 | const int RSCALE = SCALE + SCALE - 16; |
| 659 | for (; dy + 16 <= dstcols; dy += 16) { |
| 660 | int32x4_t v_cache0_0; |
| 661 | int32x4_t v_cache1_0; |
| 662 | int32x4_t v_cache0_4; |
| 663 | int32x4_t v_cache1_4; |
| 664 | int32x4_t v_cache0_8; |
| 665 | int32x4_t v_cache1_8; |
| 666 | int32x4_t v_cache0_c; |
| 667 | int32x4_t v_cache1_c; |
| 668 | |
| 669 | v_cache0_0 = vld1q_s32(cache0_ptr + dy + 0x0); |
| 670 | v_cache1_0 = vld1q_s32(cache1_ptr + dy + 0x0); |
| 671 | v_cache0_4 = vld1q_s32(cache0_ptr + dy + 0x4); |
| 672 | v_cache1_4 = vld1q_s32(cache1_ptr + dy + 0x4); |
| 673 | v_cache0_8 = vld1q_s32(cache0_ptr + dy + 0x8); |
| 674 | v_cache1_8 = vld1q_s32(cache1_ptr + dy + 0x8); |
| 675 | v_cache0_c = vld1q_s32(cache0_ptr + dy + 0xc); |
| 676 | v_cache1_c = vld1q_s32(cache1_ptr + dy + 0xc); |
| 677 | |
| 678 | int16x4_t v_ans0, v_ans4, v_ans8, v_ansc; |
| 679 | v_ans0 = vqshrn_n_s32( |
| 680 | vmlaq_s32(vmulq_s32(v_rx, v_cache1_0), v_irx, v_cache0_0), 16); |
| 681 | v_ans4 = vqshrn_n_s32( |
| 682 | vmlaq_s32(vmulq_s32(v_rx, v_cache1_4), v_irx, v_cache0_4), 16); |
| 683 | v_ans8 = vqshrn_n_s32( |
| 684 | vmlaq_s32(vmulq_s32(v_rx, v_cache1_8), v_irx, v_cache0_8), 16); |
| 685 | v_ansc = vqshrn_n_s32( |
no test coverage detected