| 158 | } |
| 159 | |
| 160 | void SPIClass::notUsingInterrupt(uint8_t interruptNumber) |
| 161 | { |
| 162 | // Once in mode 2 we can't go back to 0 without a proper reference count |
| 163 | if (interruptMode == 2) |
| 164 | return; |
| 165 | uint8_t mask = 0; |
| 166 | uint8_t sreg = SREG; |
| 167 | noInterrupts(); // Protect from a scheduler and prevent transactionBegin |
| 168 | switch (interruptNumber) { |
| 169 | #ifdef SPI_INT0_MASK |
| 170 | case 0: mask = SPI_INT0_MASK; break; |
| 171 | #endif |
| 172 | #ifdef SPI_INT1_MASK |
| 173 | case 1: mask = SPI_INT1_MASK; break; |
| 174 | #endif |
| 175 | #ifdef SPI_INT2_MASK |
| 176 | case 2: mask = SPI_INT2_MASK; break; |
| 177 | #endif |
| 178 | #ifdef SPI_INT3_MASK |
| 179 | case 3: mask = SPI_INT3_MASK; break; |
| 180 | #endif |
| 181 | #ifdef SPI_INT4_MASK |
| 182 | case 4: mask = SPI_INT4_MASK; break; |
| 183 | #endif |
| 184 | #ifdef SPI_INT5_MASK |
| 185 | case 5: mask = SPI_INT5_MASK; break; |
| 186 | #endif |
| 187 | #ifdef SPI_INT6_MASK |
| 188 | case 6: mask = SPI_INT6_MASK; break; |
| 189 | #endif |
| 190 | #ifdef SPI_INT7_MASK |
| 191 | case 7: mask = SPI_INT7_MASK; break; |
| 192 | #endif |
| 193 | default: |
| 194 | break; |
| 195 | // this case can't be reached |
| 196 | } |
| 197 | interruptMask &= ~mask; |
| 198 | if (!interruptMask) |
| 199 | interruptMode = 0; |
| 200 | SREG = sreg; |
| 201 | } |
nothing calls this directly
no outgoing calls
no test coverage detected