Initialize memory-mapped UART interface
(&mut self)
| 35 | |
| 36 | // Initialize memory-mapped UART interface |
| 37 | pub fn init(&mut self) |
| 38 | { |
| 39 | let self_inten = self.inten.load(Ordering::Relaxed); |
| 40 | let self_lnctl = self.lnctl.load(Ordering::Relaxed); |
| 41 | let self_data = self.data.load(Ordering::Relaxed); |
| 42 | let self_fifoctl = self.fifoctl.load(Ordering::Relaxed); |
| 43 | let self_modemctl = self.modemctl.load(Ordering::Relaxed); |
| 44 | unsafe |
| 45 | { |
| 46 | // Disable interrupts: |
| 47 | self_inten.write(0x00); |
| 48 | // Enable DLAB: |
| 49 | self_lnctl.write(0x80); |
| 50 | // Configure DLL/DLM to set maximum speed to 38400 b/s: |
| 51 | self_data.write(0x03); |
| 52 | self_inten.write(0x00); |
| 53 | // Disable DLAB, set data word-length to 8 bits: |
| 54 | self_lnctl.write(0x03); |
| 55 | // Enable FIFO, clear TX/RX queues, set interrupt watermark to 14 bytes: |
| 56 | self_fifoctl.write(0xC7); |
| 57 | // Declare data as being ready for the terminal, request permission to send, enable aux. output number 2 as CPU interrupt line: |
| 58 | self_modemctl.write(0x0B); |
| 59 | // Enable interrupts: |
| 60 | self_inten.write(0x01); |
| 61 | } |
| 62 | } |
| 63 | |
| 64 | fn lnstat(&mut self) -> LineStatFlag |
| 65 | { |