Set attribute control register
(idx: u8, val: u8)
| 772 | |
| 773 | // Set attribute control register |
| 774 | fn set_attributectl_reg(idx: u8, val: u8) |
| 775 | { |
| 776 | interrupts::without_interrupts(|| |
| 777 | { |
| 778 | // Input status register |
| 779 | let mut isr: Port<u8> = Port::new(INPUT_STATUS_REG); |
| 780 | |
| 781 | // Address |
| 782 | let mut address: Port<u8> = Port::new(ATTRIBUTE_ADDRESS_DATA_REG); |
| 783 | |
| 784 | unsafe |
| 785 | { |
| 786 | // Reset to address mode |
| 787 | isr.read(); |
| 788 | let tmp = address.read(); |
| 789 | address.write(idx); |
| 790 | address.write(val); |
| 791 | address.write(tmp); |
| 792 | } |
| 793 | }) |
| 794 | } |
| 795 | |
| 796 | |
| 797 | // Set color |