Get attribute control register
(idx: u8)
| 730 | |
| 731 | // Get attribute control register |
| 732 | fn get_attributectl_reg(idx: u8) -> u8 |
| 733 | { |
| 734 | interrupts::without_interrupts(|| |
| 735 | { |
| 736 | // Input status register |
| 737 | let mut isr: Port<u8> = Port::new(INPUT_STATUS_REG); |
| 738 | |
| 739 | // Address |
| 740 | let mut address: Port<u8> = Port::new(ATTRIBUTE_ADDRESS_DATA_REG); |
| 741 | |
| 742 | // Data |
| 743 | let mut data: Port<u8> = Port::new(ATTRIBUTE_DATA_READ_REG); |
| 744 | |
| 745 | // Set the palette address source bit |
| 746 | let idx = idx| 0x20; |
| 747 | |
| 748 | unsafe |
| 749 | { |
| 750 | // Reset to address mode |
| 751 | isr.read(); |
| 752 | let tmp = address.read(); |
| 753 | address.write(idx); |
| 754 | let res = data.read(); |
| 755 | address.write(tmp); |
| 756 | res |
| 757 | } |
| 758 | }) |
| 759 | } |
| 760 | |
| 761 | |
| 762 | // Print formatting |