| 55 | } |
| 56 | |
| 57 | void NVMeQueue::SubmitWait(NVMeCommand& cmd, NVMeCompletion& complet){ |
| 58 | acquireLock(&queueLock); |
| 59 | cmd.commandID = nextCommandID++; |
| 60 | |
| 61 | submissionQueue[sqTail] = cmd; |
| 62 | |
| 63 | sqTail++; |
| 64 | if(sqTail >= sqCount){ |
| 65 | sqTail = 0; |
| 66 | } |
| 67 | |
| 68 | *submissionDB = sqTail; |
| 69 | |
| 70 | while(completionCycleState == !completionQueue[cqHead].phaseTag) Scheduler::Yield(); |
| 71 | complet = completionQueue[cqHead]; |
| 72 | |
| 73 | if(++cqHead >= cqCount){ |
| 74 | cqHead = 0; |
| 75 | completionCycleState = !completionCycleState; |
| 76 | } |
| 77 | |
| 78 | *completionDB = cqHead; |
| 79 | releaseLock(&queueLock); |
| 80 | } |
| 81 | |
| 82 | Controller::Controller(PCIDevice* pciDev){ |
| 83 | pciDevice = pciDev; |
no test coverage detected