Method AllocateVector

Kernel/src/arch/x86_64/pci.cpp:239–283

uint8_t PCIDevice::AllocateVector(PCIVectors type){
	if(type & PCIVectorMSI){
		if(!msiCapable){
			Log::Error("[PCIDevice] AllocateVector: Device not MSI capable!");
		} else {
			uint8_t interrupt = IDT::ReserveUnusedInterrupt();
			if(interrupt == 0xFF){
				Log::Error("[PCIDevice] AllocateVector: Could not reserve unused interrupt (no free interrupts?)!");
				return interrupt;
			}
			
			msiCap.msiControl = (msiCap.msiControl & ~(PCI_CAP_MSI_CONTROL_MME_MASK | PCI_CAP_MSI_CONTROL_VECTOR_MASKING)) | PCI_CAP_MSI_CONTROL_SET_MME(0); // We only support one message at the moment, disable masking
			msiCap.msiControl |= 1; // Enable MSIs

			msiCap.SetData(ICR_VECTOR(interrupt) | ICR_MESSAGE_TYPE_FIXED);

			msiCap.SetAddress(GetCPULocal()->id);

			if(msiCap.msiControl & PCI_CAP_MSI_CONTROL_64){
				PCI::ConfigWriteDword(bus, slot, func, msiPtr + sizeof(uint32_t) * 3, msiCap.register3);
			}
			PCI::ConfigWriteDword(bus, slot, func, msiPtr + sizeof(uint32_t) * 2, msiCap.register2);
			PCI::ConfigWriteDword(bus, slot, func, msiPtr + sizeof(uint32_t), msiCap.register1);

			PCI::ConfigWriteWord(bus, slot, func, msiPtr + sizeof(uint16_t), msiCap.msiControl);

			return interrupt;
		}
	}

	if(type & PCIVectorLegacy){
		uint8_t irq = GetInterruptLine();
		if(irq == 0xFF){ 
			Log::Error("[PCIDevice] AllocateVector: Legacy interrupts not supported by device.");
			return 0xFF;
		} else {
			APIC::IO::MapLegacyIRQ(irq);
		}

		return IRQ0 | irq;
	}

	Log::Error("[PCIDevice] AllocateVector: Could not allocate interrupt (type %i)!", static_cast<int>(type));
	return 0xFF;
}