Function Init

Kernel/src/storage/ata.cpp:99–170

	}

	int Init(){
		if(!PCI::FindGenericDevice(ideClassCode, ideSubclass)){
			Log::Warning("[ATA] No IDE controller found!");
			return 1;
		}

		controllerPCIDevice = &PCI::GetGenericPCIDevice(ideClassCode, ideSubclass);
		assert(controllerPCIDevice->vendorID != 0xFFFF);

        Log::Info("[ATA] Initializing...");

		if(controllerPCIDevice->BarIsIOPort(0)){
			uintptr_t bar;
			if((bar = controllerPCIDevice->GetBaseAddressRegister(0))){
				port0 = bar;
			}
		}

		if(controllerPCIDevice->BarIsIOPort(1)){
			uintptr_t bar;
			if((bar = controllerPCIDevice->GetBaseAddressRegister(1))){
				port1 = bar;
			}
		}

		if(controllerPCIDevice->BarIsIOPort(2)){
			uintptr_t bar;
			if((bar = controllerPCIDevice->GetBaseAddressRegister(2))){
				controlPort0 = bar;
			}
		}

		if(controllerPCIDevice->BarIsIOPort(3)){
			uintptr_t bar;
			if((bar = controllerPCIDevice->GetBaseAddressRegister(3))){
				controlPort1 = bar;
			}
		}

		assert(controllerPCIDevice->BarIsIOPort(4));
        busMasterPort = controllerPCIDevice->GetBaseAddressRegister(4);
		controllerPCIDevice->EnableBusMastering();
		
		if(debugLevelATA >= DebugLevelNormal){
			Log::Info("[ATA] Using Ports: Primary %x, Secondary %x", port0, port1);
		}

		for(int i = 0; i < 2; i++){ // Port
			WriteControlRegister(i, 0, ReadControlRegister(i, 0) | 4); // Software Reset
			
			for(int z = 0; z < 4; z++) inportb(controlPort0);

			WriteControlRegister(i, 0, 0);

			for(int j = 0; j < 2; j++){ // Drive (master/slave)
				if(DetectDrive(i, j)){
					if(debugLevelATA >= DebugLevelNormal){
						Log::Info("Found ATA Drive: Port: %d, %s", i, j ? "slave" : "master");