Class ControllerIdentity

Kernel/include/nvme.h:231–274

		};

		struct ControllerIdentity{
			uint16_t vendorID; // PCI Vendor ID
			uint16_t subsystemVendorID; // PCI Subsystem Vendor ID
			int8_t serialNumber[20]; // ASCII encoded serial number
			int8_t modelNumber[40]; // ASCII encoded model number
			int8_t firmwareRevision[8]; // ASCII encoded firmware revision
			uint8_t recommendedArbitrationBurst;
			uint8_t ieee[3]; // IEEE Organization Unique Identifier
			uint8_t cmic; // Controller Multi-Path I/O and Namespace Sharing Capabilities
			uint8_t maximumDataTransferSize; // Maximum Data Transfer Size (2 ^ (CAP.MPSMIN * n))
			uint16_t controllerID; // NVM unique controller ID
			uint32_t version;
			uint32_t rtd3ResumeLatency;
			uint32_t rtd3EntryLatency;
			uint32_t oaes;
			uint32_t controllerAttributes;
			uint16_t rrls;
			uint8_t reserved[9];
			uint8_t controllerType;
			uint8_t fGUID[16];
			uint16_t crdt[3];
			uint8_t reserved2[122];
			uint16_t oacs;
			uint8_t acl;
			uint8_t aerl;
			uint8_t firmwareUpdates;
			uint8_t logPageAttributes;
			uint8_t errorLogPageEntries;
			uint8_t numberOfPowerStates;
			uint8_t apsta;
			uint16_t wcTemp; // Minimum temperature to report overheat
			uint16_t ccTemp; // Critical temperature threshold
			uint16_t mtfa;
			uint32_t hostMemoryBufferPreferredSize; // In 4KB Units
			uint32_t hostMemoryBufferMinimumSize; // In 4KB Units
			uint8_t unused[232]; // Our driver does not care
			uint8_t sqEntrySize; // Submission Queue Entry Size (Bits 3:0) (2 ^ n)
			uint8_t cqEntrySize; // Completion Queue Entry Size  (Bits 3:0) (2 ^ n)
			uint16_t maxCmd;
			uint32_t numNamespaces; // Number of namespaces;
			uint8_t unused2[248];
			int8_t name[256]; // UTF-8 encoded NVMe Name (null-terminated)
			uint8_t unused3[3072];
		};
		static_assert(sizeof(ControllerIdentity) == 4096);

		struct NamespaceIdentity{