Class Controller

Kernel/include/nvme.h:202–394

	};

	class Controller{
	public:
		enum DriverStatus{
			ControllerNotReady,
			ControllerError,
			ControllerReady,
		};
	private:

		enum ControllerConfigCommandSet{
			NVMeConfigCmdSetNVM = 0,
			NVMeConfigCmdSetAdminOnly = 0b111,
		};

		enum AdminCommands{
			AdminCmdDeleteIOSubmissionQueue = 0x0,
			AdminCmdCreateIOSubmissionQueue = 0x1,
			AdminCmdGetLogPage              = 0x2,	
			AdminCmdDeleteIOCompletionQueue = 0x4,
			AdminCmdCreateIOCompletionQueue = 0x5,
			AdminCmdIdentify				= 0x6,
		};

		enum ControllerType{
			IOController = 1,
			DiscoveryController = 2,
			AdminController = 3,
		};

		struct ControllerIdentity{
			uint16_t vendorID; // PCI Vendor ID
			uint16_t subsystemVendorID; // PCI Subsystem Vendor ID
			int8_t serialNumber[20]; // ASCII encoded serial number
			int8_t modelNumber[40]; // ASCII encoded model number
			int8_t firmwareRevision[8]; // ASCII encoded firmware revision
			uint8_t recommendedArbitrationBurst;
			uint8_t ieee[3]; // IEEE Organization Unique Identifier
			uint8_t cmic; // Controller Multi-Path I/O and Namespace Sharing Capabilities
			uint8_t maximumDataTransferSize; // Maximum Data Transfer Size (2 ^ (CAP.MPSMIN * n))
			uint16_t controllerID; // NVM unique controller ID
			uint32_t version;
			uint32_t rtd3ResumeLatency;
			uint32_t rtd3EntryLatency;
			uint32_t oaes;
			uint32_t controllerAttributes;
			uint16_t rrls;
			uint8_t reserved[9];
			uint8_t controllerType;
			uint8_t fGUID[16];
			uint16_t crdt[3];
			uint8_t reserved2[122];
			uint16_t oacs;
			uint8_t acl;
			uint8_t aerl;
			uint8_t firmwareUpdates;
			uint8_t logPageAttributes;
			uint8_t errorLogPageEntries;
			uint8_t numberOfPowerStates;