| 38 | break; |
| 39 | |
| 40 | void BytecodeMachine::executeInstruction(RANDOMX_EXE_ARGS) { |
| 41 | switch (ibc.type) |
| 42 | { |
| 43 | INSTR_CASE(IADD_RS) |
| 44 | INSTR_CASE(IADD_M) |
| 45 | INSTR_CASE(ISUB_R) |
| 46 | INSTR_CASE(ISUB_M) |
| 47 | INSTR_CASE(IMUL_R) |
| 48 | INSTR_CASE(IMUL_M) |
| 49 | INSTR_CASE(IMULH_R) |
| 50 | INSTR_CASE(IMULH_M) |
| 51 | INSTR_CASE(ISMULH_R) |
| 52 | INSTR_CASE(ISMULH_M) |
| 53 | INSTR_CASE(INEG_R) |
| 54 | INSTR_CASE(IXOR_R) |
| 55 | INSTR_CASE(IXOR_M) |
| 56 | INSTR_CASE(IROR_R) |
| 57 | INSTR_CASE(IROL_R) |
| 58 | INSTR_CASE(ISWAP_R) |
| 59 | INSTR_CASE(FSWAP_R) |
| 60 | INSTR_CASE(FADD_R) |
| 61 | INSTR_CASE(FADD_M) |
| 62 | INSTR_CASE(FSUB_R) |
| 63 | INSTR_CASE(FSUB_M) |
| 64 | INSTR_CASE(FSCAL_R) |
| 65 | INSTR_CASE(FMUL_R) |
| 66 | INSTR_CASE(FDIV_M) |
| 67 | INSTR_CASE(FSQRT_R) |
| 68 | INSTR_CASE(CBRANCH) |
| 69 | INSTR_CASE(CFROUND) |
| 70 | INSTR_CASE(ISTORE) |
| 71 | |
| 72 | case InstructionType::NOP: |
| 73 | break; |
| 74 | |
| 75 | case InstructionType::IMUL_RCP: //executed as IMUL_R |
| 76 | default: |
| 77 | UNREACHABLE; |
| 78 | } |
| 79 | } |
| 80 | |
| 81 | void BytecodeMachine::compileInstruction(RANDOMX_GEN_ARGS) { |
| 82 | int opcode = instr.opcode; |