| 88 | tlb: crate::cpu::mmu::Tlb, |
| 89 | pub stats: PipelineStats, |
| 90 | /// Snapshot of the pipeline state produced by the most recent tick. |
| 91 | pub last_cycle: CpuPipelineFeed, |
| 92 | } |
| 93 | |
| 94 | impl Pipeline { |
| 95 | pub fn new(start_pc: u64, stack_ptr: u64) -> Self { |
| 96 | let mut regs = Registers::new(); |
| 97 | regs.pc = start_pc; |
| 98 | regs.write_x(2, stack_ptr); |
| 99 | |
| 100 | let mut csrs = CsrFile::new(); |
| 101 | csrs.mtvec = crate::rom::M_TRAP_ADDR; // _m_trap at ROM_BASE + 0x100 |
| 102 | csrs.mscratch = stack_ptr - 4096; // M-mode stack top, 4 KB below user stack |
| 103 | Self { |
| 104 | regs, |
| 105 | csrs, |
| 106 | reservation: None, |
| 107 | fetch_pc: start_pc, |
| 108 | if_id: None, |
| 109 | id_ex: None, |
| 110 | ex_mem: None, |
| 111 | mem_wb: None, |
| 112 | pending_mem_wb: None, |
| 113 | memory_wait_cycles: 0, |
| 114 | mret_in_flight: false, |
| 115 | predictor: BranchPredictor::new(), |
| 116 | tlb: crate::cpu::mmu::Tlb::new(), |
| 117 | stats: PipelineStats::default(), |
| 118 | last_cycle: CpuPipelineFeed { |
| 119 | stages: [None; 5], |
| 120 | stalled: false, |