(&mut self, addr: u64)
| 297 | a if a >= PLIC_BASE && a <= PLIC_END => Some((&mut self.plic, addr - PLIC_BASE)), |
| 298 | a if a >= FB_BASE && a <= FB_END => Some((&mut self.framebuffer, addr - FB_BASE)), |
| 299 | a if a >= KBD_BASE && a <= KBD_END => Some((&mut self.keyboard, addr - KBD_BASE)), |
| 300 | a if a >= ROM_BASE && a <= ROM_END => Some((&mut self.rom, addr)), |
| 301 | _ => { |
| 302 | // Route all RAM accesses through L1 cache (which cascades to L2, L3, then RAM) |
| 303 | Some((&mut self.l1_cache, addr)) |
| 304 | } |
| 305 | } |