Read bytes from the address space for debug inspection. ROM and MMIO are read directly. RAM is read via the cache hierarchy, which updates cache stats as a side effect (use `peek_bytes_raw` when that matters).
(&mut self, addr: u64, len: usize)
| 183 | uart, |
| 184 | clint, |
| 185 | plic, |
| 186 | framebuffer, |
| 187 | keyboard, |
| 188 | syscon_exit: None, |
| 189 | memory_latency: MemoryLatencyConfig::disabled(), |
| 190 | access_latency_cycles: 0, |
| 191 | } |
| 192 | } |
| 193 | |
| 194 | pub fn set_memory_latency_config(&mut self, config: MemoryLatencyConfig) { |
| 195 | self.memory_latency = config; |
| 196 | self.access_latency_cycles = 0; |
| 197 | } |
| 198 | |
| 199 | pub fn memory_latency_config(&self) -> MemoryLatencyConfig { |
| 200 | self.memory_latency |
| 201 | } |
| 202 | |
| 203 | /// Start one pipeline access window. Page-table and final data accesses accumulate. |
| 204 | pub fn begin_timed_access(&mut self) { |
| 205 | self.access_latency_cycles = 0; |
| 206 | } |
| 207 | |
| 208 | pub fn timed_access_cycles(&self) -> u32 { |
| 209 | self.access_latency_cycles.max(1) |
| 210 | } |
| 211 | |
| 212 | fn record_access_latency( |
| 213 | &mut self, |