Second integer source register of a decoded instruction; 0 = none.
(insn: &DecodedInsn)
| 59 | | DecodedInsn::Alu32 { rs2, .. } |
| 60 | | DecodedInsn::FStore { rs2, .. } |
| 61 | | DecodedInsn::FOp { rs2, .. } |
| 62 | | DecodedInsn::FMac { rs2, .. } |
| 63 | | DecodedInsn::Atomic { rs2, .. } => *rs2, |
| 64 | _ => 0, |
| 65 | } |
| 66 | } |
| 67 | |
| 68 | /// True when the instruction is a (potentially FP) memory load. |
| 69 | pub fn insn_is_load(insn: &DecodedInsn) -> bool { |
| 70 | matches!(insn, DecodedInsn::Load { .. } | DecodedInsn::FLoad { .. }) |
| 71 | } |
| 72 | |
| 73 | /// True when the instruction is an atomic (acts as load for hazard purposes). |
| 74 | pub fn insn_is_atomic(insn: &DecodedInsn) -> bool { |
| 75 | matches!(insn, DecodedInsn::Atomic { .. }) |
| 76 | } |