Function decode

crates/virtual-machine/src/cpu/decoder.rs:698–803

(word: u32)

            imm: u_imm(word),
        }),
        0x6F => Ok(DecodedInsn::Jal {
            rd: rd(word),
            imm: j_imm(word),
        }),
        0x67 => Ok(DecodedInsn::Jalr {
            rd: rd(word),
            rs1: rs1(word),
            imm: i_imm(word),
        }),
        0x63 => Ok(DecodedInsn::Branch {
            funct3: funct3(word),
            rs1: rs1(word),
            rs2: rs2(word),
            imm: b_imm(word),
        }),
        0x03 => Ok(DecodedInsn::Load {
            funct3: funct3(word),
            rd: rd(word),
            rs1: rs1(word),
            imm: i_imm(word),
        }),
        0x23 => Ok(DecodedInsn::Store {
            funct3: funct3(word),
            rs1: rs1(word),
            rs2: rs2(word),
            imm: s_imm(word),
        }),
        // OP-IMM: pass the full bits[31:25] as funct7 so the execute stage can
        // disambiguate SRLI vs SRAI using bit 30 (and check for illegal encodings).
        0x13 => Ok(DecodedInsn::AluImm {
            funct3: funct3(word),
            funct7: field(word, 31, 25) as u8,
            rd: rd(word),
            rs1: rs1(word),
            imm: i_imm(word),
        }),
        0x1B => Ok(DecodedInsn::AluImm32 {
            funct3: funct3(word),
            funct7: field(word, 31, 25) as u8,
            rd: rd(word),
            rs1: rs1(word),
            imm: i_imm(word),
        }),
        0x33 => Ok(DecodedInsn::Alu {
            funct3: funct3(word),
            funct7: funct7(word),
            rd: rd(word),
            rs1: rs1(word),
            rs2: rs2(word),
        }),
        0x3B => Ok(DecodedInsn::Alu32 {
            funct3: funct3(word),
            funct7: funct7(word),
            rd: rd(word),
            rs1: rs1(word),
            rs2: rs2(word),
        }),
        0x0F => decode_fence(word),