| 60 | const MIP_W_MASK: u64 = (1u64 << 1) | (1u64 << 3) | (1u64 << 5) | (1u64 << 9); |
| 61 | |
| 62 | #[derive(Clone)] |
| 63 | pub struct CsrFile { |
| 64 | // Machine-mode CSRs |
| 65 | pub mstatus: u64, |
| 66 | pub misa: u64, |
| 67 | pub medeleg: u64, |
| 68 | pub mideleg: u64, |
| 69 | pub mie: u64, |
| 70 | pub mtvec: u64, |
| 71 | pub mscratch: u64, |
| 72 | pub mepc: u64, |
| 73 | pub mcause: u64, |
| 74 | pub mtval: u64, |
| 75 | pub mip: u64, |
| 76 | // Only PMP entry 0 exists, enforced with simplified TOR-like semantics. |
| 77 | // Entries 1-15 are intentionally absent. See VM spec 4.4. |
| 78 | pub pmpcfg0: u64, |
| 79 | pub pmpaddr0: u64, |
| 80 | |
| 81 | // Supervisor-mode CSRs (truly independent S-mode registers) |
| 82 | // sstatus, sie, sip are views into mstatus, mie, mip - not stored separately. |
| 83 | pub stvec: u64, |
| 84 | pub sscratch: u64, |
| 85 | pub sepc: u64, |
| 86 | pub scause: u64, |
| 87 | pub stval: u64, |
| 88 | pub satp: u64, |
| 89 | |
| 90 | // Performance counters |
| 91 | pub cycle: u64, |
| 92 | pub instret: u64, |
| 93 | |
| 94 | // Floating-point state |
| 95 | pub fflags: u8, |
| 96 | pub frm: u8, |
| 97 | } |
| 98 | |
| 99 | impl CsrFile { |
| 100 | pub fn new() -> Self { |
nothing calls this directly
no outgoing calls
no test coverage detected