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Functions2,620 in github.com/Jamesbarford/holyc-lang

⨍ Functions 2,620◇ Types & classes 147

↓ 2 callersFunctionx86_64EmitSetCC

Materialise the EFLAGS-encoded comparison result as 0/1 in %rax. * setcc only writes the low byte, so we follow with a zero-extension * into the ful

src/x86_64.c:683

↓ 2 callersFunctionx86_64Epilogue

leaveq is `movq %rbp, %rsp; popq %rbp` in one instruction. Saves a * byte over the explicit pair, no other difference. When the matching * prologue

src/x86_64.c:734

↓ 2 callersFunctionx86_64GenerateFunction

src/x86_64.c:2244

↓ 2 callersFunctionx86_64GlobalAddr

leaq <sym>(%rip), %<reg64>. Caller has already normalised the * symbol name */

src/x86_64.c:116

↓ 2 callersFunctionx86_64InitialiseEmptyGlobal

src/x86_64.c:2336

↓ 2 callersFunctionx86_64IsXmmName

XMM register names start with x/X; GPR names never do. */

src/x86_64.c:696

↓ 2 callersFunctionx86_64Load

Width-aware load from <loff>(%rbp) into <reg64>. * * Width policy mirrors aarch64's choice: sub-word loads (1/2) zero- * extend to the full registe

src/x86_64.c:146

↓ 2 callersFunctionx86_64PinnedSaveBytes

src/x86_64.c:700

↓ 2 callersFunctionx86_64RestorePinnedRegs

src/x86_64.c:720

↓ 2 callersFunctionx86_64RmwMnem

Mnemonic base for an RMW IrOp; suffix added by caller. */

src/x86_64.c:272

↓ 2 callersFunctionx86_64StoreFpr

src/x86_64.c:555

↓ 2 callersFunctionx86_64StoreReg

Store a 64-bit GP register into the destination IrValue's home. * If the destination is pinned, this is just a register-to-register * move; otherwis

src/x86_64.c:369

↓ 2 callersFunctionx86_64_emit_branch_to_label

Helper: emit JMP/Jcc to a label operand (local @@N or symbol), or to * a numeric rel32 displacement (`jmp -5`, `je -6`) as printed by the * disassem

src/asm/enc_x86_64.c:2080

↓ 2 callersFunctionx86_64_emit_mem_fixup

Record a fixup for a memory operand's disp32. */

src/asm/enc_x86_64.c:1133

↓ 2 callersFunctionx86_64_enc_addq_imm_reg

src/asm/enc_x86_64.c:280

↓ 2 callersFunctionx86_64_enc_call_reg

src/asm/enc_x86_64.c:473

↓ 2 callersFunctionx86_64_enc_call_rel32

src/asm/enc_x86_64.c:464

↓ 2 callersFunctionx86_64_enc_cmp_reg_reg

src/asm/enc_x86_64.c:371

↓ 2 callersFunctionx86_64_enc_cmpq_imm_reg

src/asm/enc_x86_64.c:685

↓ 2 callersFunctionx86_64_enc_cvtsi2

Integer <-> floating-point conversions. These mix XMM and GPR operands * and use REX.W when the GPR is 64-bit. * * cvtsi2ss/cvtsi2sd xmm, r/m{32

src/asm/enc_x86_64.c:2026

↓ 2 callersFunctionx86_64_enc_fucom_or_fucomp

src/asm/enc_x86_64.c:2199

↓ 2 callersFunctionx86_64_enc_imul_reg_reg

src/asm/enc_x86_64.c:326

↓ 2 callersFunctionx86_64_enc_inc_dec

src/asm/enc_x86_64.c:1721

↓ 2 callersFunctionx86_64_enc_mov_mem_reg

src/asm/enc_x86_64.c:102

↓ 2 callersFunctionx86_64_enc_movx

MOVZX / MOVSX: 0F B6/B7 (zero) or 0F BE/BF (sign), 1- or 2-byte * source widening into a 2/4/8-byte register. */

src/asm/enc_x86_64.c:2253

↓ 2 callersFunctionx86_64_enc_movzx_reg_reg

movzbq / movzwq r64, r/m8|16; width 4 lowers to `movl src, dst` whose * 32-bit write zero-extends. width 8 is a plain register move. */

src/asm/enc_x86_64.c:545

↓ 2 callersFunctionx86_64_enc_ucomisd

src/asm/enc_x86_64.c:785

↓ 2 callersFunctionx86_64_enc_ucomiss

ucomiss %b, %a : 0F 2E /r (no prefix). */

src/asm/enc_x86_64.c:926

↓ 2 callersFunctionx86_64_enc_xorps

xorps %src, %dst : 0F 57 /r (no prefix). */

src/asm/enc_x86_64.c:937

↓ 2 callersFunctionx86_64_mnemonic_table

src/asm/enc_x86_64.c:2860

↓ 2 callersFunctionx86_64_patch_rel32

x86_64 rel32: signed displacement from the END of the instruction (i.e. * patch_offset + 4) to the target. +/-2GB range. Used by CALL/JMP/Jcc and *

src/asm/asm_jit.c:133

↓ 1 callersFunctionAstUpCastInt

↓ 1 callersFunction_aarch64_enc_barrier

DMB/DSB/ISB share the encoding * 1101 0101 0000 0011 0011 CRm:4 1 opc2:3 11111 * where opc2 picks the barrier kind: * DSB = 0b100 (4), DMB = 0b

src/asm/enc_arm64.c:1695

↓ 1 callersFunction_aarch64_enc_bfcvtn

src/asm/enc_arm64.c:976

↓ 1 callersFunction_aarch64_enc_fp_1src

FP scalar 1-source: FABS / FNEG / FSQRT. Encoding: * 0 0 0 11110 ftype 1 opcode6 10000 Rn Rd * * opcode6: FMOV=000000 (already), FABS=000001,

src/asm/enc_arm64.c:820

↓ 1 callersFunction_aarch64_enc_fp_int_cvt

FP <-> int conversions. Shares encoding family with FMOV reg/gpr: * sf 0 0 11110 ftype 1 [rmode:2 opcode:3] 000000 Rn Rd * * rmode<<3 | opcode

src/asm/enc_arm64.c:872

↓ 1 callersFunction_aarch64_enc_mrs

MRS Xt, sysreg : 1101 0101 0011 o0 op1 CRn CRm op2 Rt (L=1) * MSR sysreg, Xt : 1101 0101 0001 o0 op1 CRn CRm op2 Rt (L=0) * * sysreg16 is the

src/asm/enc_arm64.c:1711

↓ 1 callersFunction_astToStringRec

↓ 1 callersFunction_bbFindAllLoopNodes

↓ 1 callersFunction_memAlign

Align to 8 bytes */

src/mempool.c:104

↓ 1 callersFunctiona64JitArithInit

src/aarch64-jit.c:1091

↓ 1 callersFunctiona64JitCallInit

src/aarch64-jit.c:915

↓ 1 callersFunctiona64JitConvInit

src/aarch64-jit.c:1004

↓ 1 callersFunctiona64JitEmitInit

src/aarch64-jit.c:799

↓ 1 callersFunctiona64JitParamInit

src/aarch64-jit.c:965

↓ 1 callersFunctiona64TxtArithInit

src/aarch64.c:1163

↓ 1 callersFunctiona64TxtCallInit

src/aarch64.c:983

↓ 1 callersFunctiona64TxtConvInit

src/aarch64.c:1074

↓ 1 callersFunctiona64TxtEmitInit

src/aarch64.c:894

↓ 1 callersFunctiona64TxtIntMnem

src/aarch64.c:1102

↓ 1 callersFunctiona64TxtParamInit

src/aarch64.c:1033

↓ 1 callersFunctionaarch64AsmGenerate

src/aarch64.c:2063

↓ 1 callersFunctionaarch64CcInvFor

src/aarch64.c:666

↓ 1 callersFunctionaarch64CopyToSp

Emit an `extern "c"` call that passes one or more structs by value, * following AAPCS64. Scalars and structs are classified together so the * GP/FP

src/aarch64.c:819

↓ 1 callersFunctionaarch64DataInternal

src/aarch64.c:1947

↓ 1 callersFunctionaarch64EmitFloatLiteral

Emit a float constant to the literal pool and load it into the * target FP register. `size` selects single (4) vs double (8) * precision: an 8-byte

src/aarch64.c:374

↓ 1 callersFunctionaarch64EmitFunctionPrologue

src/aarch64.c:1830

↓ 1 callersFunctionaarch64EmitInstr

src/aarch64.c:1175

↓ 1 callersFunctionaarch64EmitOnePhi

src/aarch64.c:704

↓ 1 callersFunctionaarch64FpFrameStore

src/aarch64.c:261

↓ 1 callersFunctionaarch64GlobalVar

src/aarch64.c:1979

↓ 1 callersFunctionaarch64HasRet

Did the last emit already place an epilogue at the tail of buf? Lets * IR_RET emit the epilogue inline (no jump-to-end-label dance) while * the func

src/aarch64.c:1869

↓ 1 callersFunctionaarch64InitRegPool

src/aarch64.c:57

↓ 1 callersFunctionaarch64JitCompile

src/aarch64-jit.c:26

↓ 1 callersFunctionaarch64PartitionCallArgs

HolyC variadic args go on the stack starting at sp+0, not in * argument registers, so the callee can index them as a contiguous * argv region. Retur

src/aarch64.c:783

↓ 1 callersFunctionaarch64PasteAsmBlocks

`asm {}` function blocks, encoded to bytes by libtasm. External * symbol references can't be expressed as `.byte` runs on arm64 (the * relocation la

src/aarch64.c:2045

↓ 1 callersFunctionaarch64PasteDataSection

src/aarch64.c:1822

↓ 1 callersFunctionaarch64PasteDataSectionDarwin

src/aarch64.c:1796

↓ 1 callersFunctionaarch64PasteDataSectionLinux

src/aarch64.c:1809

↓ 1 callersFunctionaarch64_barrier_option_from_name

Map a DMB/DSB option name (case-insensitive) to its 4-bit CRm value. * Returns -1 if unknown. */

src/asm/enc_arm64.c:3330

↓ 1 callersFunctionaarch64_disasm_buf

src/asm/dis_arm64.c:1782

↓ 1 callersFunctionaarch64_emit_b_cond_local

Emit a B.cond to a local label, adding an IMM19 fixup. We tag fixups for * 19-bit displacements via width=19 so the resolver picks the right patcher

src/asm/enc_arm64.c:1837

↓ 1 callersFunctionaarch64_emit_branch_local

Emit a B/BL to a local label, adding a BRANCH26 fixup. */

src/asm/enc_arm64.c:1819

↓ 1 callersFunctionaarch64_emit_veneer

The bytes we drop into the executable mapping must match what * `aarch64_jit_emit_trampoline` would have emitted into an AsmEnc. * Routing through a

src/asm/asm_jit.c:210

↓ 1 callersFunctionaarch64_enc_adrp_dispatch

ADRP Xd, _sym * * Loads the page address of `_sym` (bits 12 and up of the symbol's * address minus the PC's page) into Xd. Always paired with an `a

src/asm/enc_arm64.c:3629

↓ 1 callersFunctionaarch64_enc_asr_imm

ASR (immediate) - SBFM alias: SBFM <Rd>, <Rn>, #shift, #(regsize - 1). */

src/asm/enc_arm64.c:1565

↓ 1 callersFunctionaarch64_enc_bfcvt_scalar

BFCVT Hd, Sn - scalar fp32 -> bf16. */

src/asm/enc_arm64.c:2753

↓ 1 callersFunctionaarch64_enc_bfdot

BFDOT V<d>.<2S|4S>, V<n>.<4H|8H>, V<m>.<4H|8H> * - Q=0 form: V<d>.2S, V<n>.4H, V<m>.4H * - Q=1 form: V<d>.4S, V<n>.8H, V<m>.8H * * Indexed for

src/asm/enc_arm64.c:2664

↓ 1 callersFunctionaarch64_enc_bfmmla

BFMMLA Vd.4S, Vn.8H, Vm.8H */

src/asm/enc_arm64.c:2734

↓ 1 callersFunctionaarch64_enc_cmp

src/asm/enc_arm64.c:2097

↓ 1 callersFunctionaarch64_enc_fcvt_narrow

FCVT Sd, Dn - narrow double to single. */

src/asm/enc_arm64.c:433

↓ 1 callersFunctionaarch64_enc_fcvt_widen

FCVT Dd, Sn - widen single to double. */

src/asm/enc_arm64.c:443

↓ 1 callersFunctionaarch64_enc_fcvtzs

FCVTZS <Rd>, <Fn> (rmode=11, opcode=000). */

src/asm/enc_arm64.c:470

↓ 1 callersFunctionaarch64_enc_fcvtzu

FCVTZU <Rd>, <Fn> (rmode=11, opcode=001). */

src/asm/enc_arm64.c:477

↓ 1 callersFunctionaarch64_enc_fmov

FMOV dispatch. Recognises the scalar/imm/GPR-swap forms. */

src/asm/enc_arm64.c:2786

↓ 1 callersFunctionaarch64_enc_fneg_scalar

FNEG (scalar): 0 0 0 11110 ftype 1 000010 10000 Rn Rd. */

src/asm/enc_arm64.c:403

↓ 1 callersFunctionaarch64_enc_ldp_post

src/asm/enc_arm64.c:1143

↓ 1 callersFunctionaarch64_enc_lsl

LSL <Rd>, <Rn>, #imm - UBFM alias (immediate shift) * LSL <Rd>, <Rn>, <Rm> - LSLV (variable shift) */

src/asm/enc_arm64.c:2055

↓ 1 callersFunctionaarch64_enc_lsr_imm

LSR (immediate) - UBFM alias: UBFM <Rd>, <Rn>, #shift, #(regsize - 1). */

src/asm/enc_arm64.c:1550

↓ 1 callersFunctionaarch64_enc_mov

src/asm/enc_arm64.c:1871

↓ 1 callersFunctionaarch64_enc_mov_imm32

src/asm/enc_arm64.c:119

↓ 1 callersFunctionaarch64_enc_mrs

src/asm/enc_arm64.c:3487

↓ 1 callersFunctionaarch64_enc_msr

src/asm/enc_arm64.c:3504

↓ 1 callersFunctionaarch64_enc_mulm

src/asm/enc_arm64.c:2041

↓ 1 callersFunctionaarch64_enc_neg

src/asm/enc_arm64.c:2084

↓ 1 callersFunctionaarch64_enc_patch_branch26

Patch a branch now that we know where we are going */

src/asm/enc_arm64.c:1244

↓ 1 callersFunctionaarch64_enc_patch_imm19

src/asm/enc_arm64.c:1273

↓ 1 callersFunctionaarch64_enc_printreg

---------- PRINTREG (debug helper, calls a C-side runtime) ---------- * * `PRINTREG <reg>` expands to a save-args / setup / BL <helper> / * restore

src/asm/enc_arm64.c:2499

↓ 1 callersFunctionaarch64_enc_scvtf

SCVTF <Fd>, <Rn> (rmode=00, opcode=010). */

src/asm/enc_arm64.c:484

↓ 1 callersFunctionaarch64_enc_sdi

src/asm/enc_arm64.c:2047

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