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Functions2,620 in github.com/Jamesbarford/holyc-lang

⨍ Functions 2,620◇ Types & classes 147

↓ 3 callersFunctionprsAsm

The next token is expected to be '{'; the parser has just seen `asm`. */

src/prsasm.c:151

↓ 3 callersFunctionprsAsmTasmArch

src/prsasm.c:41

↓ 3 callersFunctionsetIterRelease

src/containers.c:571

↓ 3 callersFunctionstrtab_add

src/asm/macho.c:214

↓ 3 callersFunctiontest_asm_enc_free

src/asm/test-helper.c:39

↓ 3 callersFunctiontest_ctx_init

src/asm/test-helper.c:46

↓ 3 callersFunctiontokenRingBufferEmpty

src/cctrl.c:356

↓ 3 callersFunctiontokenRingBufferPeek

src/cctrl.c:395

↓ 3 callersFunctiontranspileFormatFunction

make lower camelcase */

src/transpiler.c:316

↓ 3 callersFunctiontranspileFunctionProto

src/transpiler.c:1276

↓ 3 callersFunctiontranspileHighlightChar

src/transpiler.c:377

↓ 3 callersFunctiontranspileTypeInternal

src/transpiler.c:1130

↓ 3 callersFunctiontypeCheckWarn

src/prsutil.c:500

↓ 3 callersFunctionvecClear

src/containers.c:210

↓ 3 callersFunctionvecReserve

src/containers.c:80

↓ 3 callersFunctionx86_64AggInRegs

True when the whole aggregate still fits in the remaining argument * registers; otherwise it is passed on the stack by value. */

src/x86_64.c:950

↓ 3 callersFunctionx86_64DerefStoreWidth

Width-aware store of <reg64> into `disp(<base_reg>[, <idx_reg>, * scale])`. idx_reg==NULL drops the SIB component. */

src/x86_64.c:242

↓ 3 callersFunctionx86_64GenericStoreWidth

src/x86_64.c:211

↓ 3 callersFunctionx86_64GetSizedMov

src/x86_64.c:201

↓ 3 callersFunctionx86_64IdxReg

Resolve a mem op's SIB idx to its physical register: use idx.loc * when set, otherwise load into %rdx. NULL if no scaled-idx. */

src/x86_64.c:612

↓ 3 callersFunctionx86_64IsByvalStruct

src/x86_64.c:921

↓ 3 callersFunctionx86_64MakeAoStrVec

Build AoStr-wrapped backend pool once, lazily, and hand it to the * IR layer via `irRegPoolSet`. The AoStr instances live for the * compiler's lifet

src/x86_64.c:47

↓ 3 callersFunctionx86_64RegForWidth

Map a 64-bit GP register name to its narrower variant. The * heterogeneous register-naming scheme on x86 makes this a lookup * table rather than a n

src/x86_64.c:77

↓ 3 callersFunctionx86_64_disasm

src/asm/dis_x86_64.c:832

↓ 3 callersFunctionx86_64_emit_sse_rr

Emit prefix -> REX -> 0F -> opcode -> ModRM for an xmm-xmm pair. * `is_64` adds REX.W (used by integer conversions). */

src/asm/enc_x86_64.c:1956

↓ 3 callersFunctionx86_64_enc_alu_reg_reg

src/asm/enc_x86_64.c:272

↓ 3 callersFunctionx86_64_enc_ret

ret / ret imm16 (callee-pops). RET1 is Terry's mnemonic for `ret imm16`. */

src/asm/enc_x86_64.c:1688

↓ 3 callersFunctionx86_64_enc_shift

shl/shr/sar reg, imm or reg, %cl */

src/asm/enc_x86_64.c:1477

↓ 3 callersFunctionx86_64_enc_subq_imm_reg

src/asm/enc_x86_64.c:295

↓ 3 callersFunctionx86_64_enc_x87_mem_or_reg

Helper for the common pattern: instruction takes either an x87 reg ST(i) * (encoded as op1 op2_base+i) or a memory operand of either m32 or m64 form

src/asm/enc_x86_64.c:1743

↓ 3 callersFunctionx86_64_enc_xor32_reg

src/asm/enc_x86_64.c:527

↓ 3 callersFunctionx86_64_enc_xorpd

src/asm/enc_x86_64.c:796

↓ 3 callersFunctionxmm_name

src/asm/dis_x86_64.c:440

↓ 2 callersFunction_aarch64_enc_cbz

CBZ / CBNZ - compare and branch (if zero / non-zero). Encoding: * sf 011010 op imm19 Rt * * sf=1 for X, sf=0 for W. op=0 for CBZ, 1 for CBNZ.

src/asm/enc_arm64.c:804

↓ 2 callersFunction_aoStrAlloc

src/aostr.c:131

↓ 2 callersFunctiona64EmitArith

src/aarch64-emit.h:480

↓ 2 callersFunctiona64EmitCall

src/aarch64-emit.h:91

↓ 2 callersFunctiona64EmitConvert

src/aarch64-emit.h:375

↓ 2 callersFunctiona64EmitParamPrologue

src/aarch64-emit.h:269

↓ 2 callersFunctiona64EmitStore

src/aarch64-emit.h:32

↓ 2 callersFunctiona64IsByvalStruct

--------------------------------------------------------------------------- * Unified AAPCS callee param prologue (the mirror of a64EmitCall). * *

src/aarch64-emit.h:250

↓ 2 callersFunctiona64TxtShiftMnem

src/aarch64.c:1134

↓ 2 callersFunctionaarch64AddSubImm

Emit `reg += disp` honouring the AArch64 imm12 (optionally lsl 12) * restriction. Anything wider materialises through x9. */

src/aarch64.c:274

↓ 2 callersFunctionaarch64CcFor

Condition codes for branches. AArch64 uses the same suffixes as * x86's jCC; mapping is straightforward. */

src/aarch64.c:637

↓ 2 callersFunctionaarch64CopyToSlot

Copy `size` bytes from [base_reg, #src] to [x29, #dst] using x10 as a * scratch register (8/4/2/1-byte chunks). Both src and dst are signed * displa

src/aarch64.c:846

↓ 2 callersFunctionaarch64EmitCSet

Emit a cset into x0 setting it to 1 or 0 based on the last cmp. */

src/aarch64.c:694

↓ 2 callersFunctionaarch64Epilogue

src/aarch64.c:1851

↓ 2 callersFunctionaarch64FpFrameLoad

src/aarch64.c:250

↓ 2 callersFunctionaarch64FrameLoad

src/aarch64.c:211

↓ 2 callersFunctionaarch64FrameStore

src/aarch64.c:233

↓ 2 callersFunctionaarch64GenerateFunction

src/aarch64.c:1879

↓ 2 callersFunctionaarch64InitialiseEmptyGlobal

src/aarch64.c:1930

↓ 2 callersFunctionaarch64IsLogicalImm

True if `imm` is encodable as an AArch64 logical bitmask immediate * (rotation of N consecutive 1-bits, repeated at 2/4/8/16/32/64 bit * element siz

src/aarch64.c:597

↓ 2 callersFunctionaarch64StoreFpr

src/aarch64.c:568

↓ 2 callersFunctionaarch64StoreFprSized

`val_size` is the byte width of the value being stored (0 = derive * from `dst`). An FP store writes the value's width, which differs from * `dst`'s

src/aarch64.c:546

↓ 2 callersFunctionaarch64StoreReg

src/aarch64.c:470

↓ 2 callersFunctionaarch64_add_sub_imm

ADD/SUB (immediate). Encoding: * sf | op | S | 1 0 0 0 1 0 | sh | imm12 | Rn | Rd * sf: 0 = W (32-bit), 1 = X (64-bit). * op: 0 = ADD, 1 = SUB.

src/asm/enc_arm64.c:165

↓ 2 callersFunctionaarch64_enc_add_reg_shifted

Shifted-register variants exposed for the dispatcher. */

src/asm/enc_arm64.c:239

↓ 2 callersFunctionaarch64_enc_add_sub

src/asm/enc_arm64.c:1946

↓ 2 callersFunctionaarch64_enc_asrv

src/asm/enc_arm64.c:1585

↓ 2 callersFunctionaarch64_enc_bfcvt

src/asm/enc_arm64.c:967

↓ 2 callersFunctionaarch64_enc_bfcvtn

BFCVTN Vd.4H, Vn.4S * BFCVTN2 Vd.8H, Vn.4S */

src/asm/enc_arm64.c:2771

↓ 2 callersFunctionaarch64_enc_bfmlal

BFMLALB / BFMLALT Vd.4S, Vn.8H, Vm.8H - output is always full 4S. */

src/asm/enc_arm64.c:2718

↓ 2 callersFunctionaarch64_enc_bfmlalb

src/asm/enc_arm64.c:947

↓ 2 callersFunctionaarch64_enc_bfmlalt

src/asm/enc_arm64.c:957

↓ 2 callersFunctionaarch64_enc_br_blr

src/asm/enc_arm64.c:3611

↓ 2 callersFunctionaarch64_enc_cbz

CBZ / CBNZ Rt, label * Local @@N labels resolve via the same imm19 path as B.cond. */

src/asm/enc_arm64.c:2936

↓ 2 callersFunctionaarch64_enc_fcmp

FCMP / FCMPE, supports register form and zero (FP-immediate 0.0) form. */

src/asm/enc_arm64.c:3017

↓ 2 callersFunctionaarch64_enc_fcmp_reg2

FCMP (scalar, register): 0 0 0 11110 ftype 1 Rm 001000 Rn 00000. */

src/asm/enc_arm64.c:414

↓ 2 callersFunctionaarch64_enc_fcmp_zero

FCMP (scalar, zero): as register form with Rm=0 and opcode2 bit 3 set. */

src/asm/enc_arm64.c:425

↓ 2 callersFunctionaarch64_enc_fmov_imm

src/asm/enc_arm64.c:1058

↓ 2 callersFunctionaarch64_enc_fmov_reg_h

FMOV Hd, Hn - half-precision scalar copy (FEAT_FP16, type=11). */

src/asm/enc_arm64.c:1034

↓ 2 callersFunctionaarch64_enc_ldrsb_imm

Signed loads. opc=10 sign-extends to X (64-bit dst), opc=11 to W (32-bit). * LDRSW only has an X-destination form. */

src/asm/enc_arm64.c:1341

↓ 2 callersFunctionaarch64_enc_ldrsh_imm

src/asm/enc_arm64.c:1347

↓ 2 callersFunctionaarch64_enc_ldst64

LDR/STR (64-bit GPR). Now also handles pre-index / post-index and * register-offset forms in addition to the original unsigned-offset. * * Forms re

src/asm/enc_arm64.c:2127

↓ 2 callersFunctionaarch64_enc_ldst_unscaled_mn

LDUR / STUR spelled explicitly: `ldur Rt, [Xn, #simm9]`. Same word * `ldr`/`str` fall back to for negative or misaligned offsets, but with * no scal

src/asm/enc_arm64.c:3582

↓ 2 callersFunctionaarch64_enc_lsrv

src/asm/enc_arm64.c:1579

↓ 2 callersFunctionaarch64_enc_mov_imm

src/asm/enc_arm64.c:91

↓ 2 callersFunctionaarch64_enc_mov_reg_base

src/asm/enc_arm64.c:126

↓ 2 callersFunctionaarch64_enc_movn

src/asm/enc_arm64.c:85

↓ 2 callersFunctionaarch64_enc_msr_reg

src/asm/enc_arm64.c:1720

↓ 2 callersFunctionaarch64_enc_msub

src/asm/enc_arm64.c:1494

↓ 2 callersFunctionaarch64_enc_mul

src/asm/enc_arm64.c:1488

↓ 2 callersFunctionaarch64_enc_mvn_reg

src/asm/enc_arm64.c:1598

↓ 2 callersFunctionaarch64_enc_simd_ldst

LDR/STR for SIMD/FP scalar registers (B/H/S/D/Q). * Handles unsigned-offset, pre-index, post-index, and register-offset forms. */

src/asm/enc_arm64.c:3169

↓ 2 callersFunctionaarch64_enc_stp_pre

src/asm/enc_arm64.c:1137

↓ 2 callersFunctionaarch64_enc_sub_reg_shifted

src/asm/enc_arm64.c:253

↓ 2 callersFunctionaarch64_enc_subs_imm

SUBS (subtract, set flags). Two variants: * - immediate: sf op=1 S=1 100010 sh imm12 Rn Rd (sh=0 only here) * - shifted reg: sf op=1 S

src/asm/enc_arm64.c:621

↓ 2 callersFunctionaarch64_enc_subs_reg

src/asm/enc_arm64.c:634

↓ 2 callersFunctionaarch64_enc_udiv

src/asm/enc_arm64.c:1519

↓ 2 callersFunctionaarch64_extract_shift_suffix

Pull an optional 4th `LSL/LSR/ASR #N` operand off the line. Writes * *out_type and *out_amount; returns 1 if a valid shift was found, 0 * if there

src/asm/enc_arm64.c:1919

↓ 2 callersFunctionaarch64_jit_emit_bl_placeholder

src/asm/enc_arm64.c:3676

↓ 2 callersFunctionaarch64_jit_emit_ret

src/asm/enc_arm64.c:3669

↓ 2 callersFunctionaarch64_ldp_stp

LDP/STP (pair, 64-bit). Index modes: * pre-indexed : opc=10 | 1 0 1 | V=0 | 1 0 0 | L | imm7 | Rt2 | Rn | Rt * post-indexed : opc=10 | 1 0 1 |

src/asm/enc_arm64.c:1118

↓ 2 callersFunctionaarch64_ldst_uimm

LDR/STR (unsigned offset), 64-bit: * bits 31:24 = 11111001 (0xF9) * bits 23:22 = opc (00 STR, 01 LDR) * bits 21:10 = imm12 (offset / 8, in 8-

src/asm/enc_arm64.c:328

↓ 2 callersFunctionaarch64_local_label_num

Detect a `@@N`-style label name and return its number, or -1 otherwise. * Mirrors the x86 path's operand_local_num. */

src/asm/enc_arm64.c:2925

↓ 2 callersFunctionaarch64_patch_branch26

AArch64 BL/B: top byte is 0x94 (BL) or 0x14 (B); low 26 bits are a signed * word-count displacement. +/-128MB range. */

src/asm/asm_jit.c:98

↓ 2 callersFunctionaarch64_size_for_width

src/asm/enc_arm64.c:1413

↓ 2 callersFunctionaarch64_sysreg_from_name

Lookup table of EL0-accessible named system registers. Add entries on * demand; the generic `S<op0>_<op1>_C<n>_C<m>_<op2>` escape covers the * long

src/asm/enc_arm64.c:3402

↓ 2 callersFunctionaarch64_sysreg_pack

Pack op0|op1|CRn|CRm|op2 into the 16-bit sysreg field used by MRS/MSR. * `op0` is 2 or 3 (only its low bit is encoded in `o0`). */

src/asm/enc_arm64.c:3389

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