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Functions2,620 in github.com/Jamesbarford/holyc-lang

⨍ Functions 2,620◇ Types & classes 147

↓ 5 callersFunctionx86_64_enc_movq_xmm_gpr

movq %xmm, %gpr : 66 REX.W 0F 7E /r. */

src/asm/enc_x86_64.c:775

↓ 5 callersFunctionx86_64_enc_movsd_load

src/asm/enc_x86_64.c:739

↓ 5 callersFunctionx86_64_enc_movss_load

src/asm/enc_x86_64.c:877

↓ 5 callersFunctionx86_64_sib

src/asm/enc_x86_64.c:974

↓ 4 callersFunctionCalcPadding

src/parser.c:421

↓ 4 callersFunction_astLValueToString

This can only be used for lvalues */

↓ 4 callersFunctionaarch64FpRegForWidth

Adjust an FP register name (dN) to the right precision for `size`. * 8 bytes -> dN (double), 4 bytes -> sN (float). */

src/aarch64.c:98

↓ 4 callersFunctionaarch64FrameOperand

Pick the addressing form for a frame access. AArch64 ldr/str * scaled-imm wants non-negative offsets in size-multiples; ldur/stur * supports signed

src/aarch64.c:180

↓ 4 callersFunctionaarch64_disasm

src/asm/dis_arm64.c:1768

↓ 4 callersFunctionaarch64_enc_b

B / BL (unconditional immediate): * op | 0 0 1 0 1 | imm26 - op=0 for B, op=1 for BL. */

src/asm/enc_arm64.c:1168

↓ 4 callersFunctionaarch64_enc_b_cond

B.cond: 0101 0100 | imm19 | 0 | cond(4). */

src/asm/enc_arm64.c:1197

↓ 4 callersFunctionaarch64_enc_bfdot_idx

src/asm/enc_arm64.c:929

↓ 4 callersFunctionaarch64_enc_bl

src/asm/enc_arm64.c:1175

↓ 4 callersFunctionaarch64_enc_blr

src/asm/enc_arm64.c:1190

↓ 4 callersFunctionaarch64_enc_cset

src/asm/enc_arm64.c:1667

↓ 4 callersFunctionaarch64_enc_fmov_h_gpr

FMOV W<->H - GPR/FP bridge for the bf16 widen sequence. * `fp_to_gpr=1` -> `FMOV Wd, Hn`; `fp_to_gpr=0` -> `FMOV Hd, Wn`. */

src/asm/enc_arm64.c:1045

↓ 4 callersFunctionaarch64_enc_fp_arith

FADD/FSUB/FMUL/FDIV dispatch - works on either scalar SIMD regs * (S0,S1,S2 / D0,D1,D2) or V-form vectors (V0.4S etc.). `op` selects * the instruct

src/asm/enc_arm64.c:2406

↓ 4 callersFunctionaarch64_enc_fp_int_cvt

FP <-> int conversions. Picks (sf, ftype) from the operand widths and * (rmode_opcode5) from the mnemonic family. */

src/asm/enc_arm64.c:3050

↓ 4 callersFunctionaarch64_enc_ldp_stp

LDP/STP and LDNP/STNP - load/store pair. Three operands: Rt1, Rt2, [mem]. * * Pair widths: W/X for GPRs, S/D/Q for SIMD. When `nontemporal` is set

src/asm/enc_arm64.c:2871

↓ 4 callersFunctionaarch64_enc_ldst_post

src/asm/enc_arm64.c:700

↓ 4 callersFunctionaarch64_enc_ldst_pre

src/asm/enc_arm64.c:712

↓ 4 callersFunctionaarch64_enc_ldst_sub

LDRB/STRB/LDRH/STRH dispatch. The destination/source must be a W * register; `width` is 1 (byte) or 2 (halfword). Supports the same * address forms

src/asm/enc_arm64.c:2207

↓ 4 callersFunctionaarch64_enc_movk

src/asm/enc_arm64.c:79

↓ 4 callersFunctionaarch64_enc_orr_reg

src/asm/enc_arm64.c:1459

↓ 4 callersFunctionaarch64_enc_stur

src/asm/enc_arm64.c:1430

↓ 4 callersFunctionaarch64_enc_sxtw

src/asm/enc_arm64.c:314

↓ 4 callersFunctionaarch64_enc_uxth

UXTH Wd, Wn = UBFM Wd, Wn, #0, #15. */

src/asm/enc_arm64.c:283

↓ 4 callersFunctionaarch64_fp_int_cvt

FP<->integer conversions. Encoding: * sf 0 0 11110 ftype 1 rmode opcode 000000 Rn Rd * `is_64` selects the X(1) vs W(0) GPR; `fp_is_double` selec

src/asm/enc_arm64.c:456

↓ 4 callersFunctionaarch64_mov_wide

MOVZ / MOVK / MOVN share the wide-immediate encoding layout: * sf | opc(2) | 1 0 0 1 0 1 | hw(2) | imm16(16) | Rd(5) * * opc: 00 = MOVN, 10 = MOV

src/asm/enc_arm64.c:62

↓ 4 callersFunctionaarch64_read_word

src/asm/enc_arm64.c:1223

↓ 4 callersFunctionaarch64_write_word

src/asm/enc_arm64.c:1233

↓ 4 callersFunctionaoStrCmp

src/aostr.c:226

↓ 4 callersFunctionaoStrIntToHumanReadableBytes

src/aostr.c:741

↓ 4 callersFunctionaoStrPrintfVa

src/aostr.c:547

↓ 4 callersFunctionasmCast

↓ 4 callersFunctionasmEmitBlockBytes

↓ 4 callersFunctionasm_enc_set_error_handler

src/asm/asm_enc.c:284

↓ 4 callersFunctionastAsmFunctionCall

↓ 4 callersFunctionastClassType

↓ 4 callersFunctionastIsRangeOperator

↓ 4 callersFunctionastKindToHumanReadable

↓ 4 callersFunctionastTypeAlign

Alignment of a type: scalars/pointers by their width (<=8), arrays by * their element, classes/unions by the alignment recorded during their * own l

↓ 4 callersFunctionastTypeMapNew

↓ 4 callersFunctionastUnOpKindToString

↓ 4 callersFunctionbbIsLoopEnd

↓ 4 callersFunctionbbSetElse

↓ 4 callersFunctionbbSetIf

↓ 4 callersFunctionblock_push

src/asm/asm.c:669

↓ 4 callersFunctioncc_name

src/asm/dis_x86_64.c:231

↓ 4 callersFunctioncctrlGetOrSetString

De-duplicates strings by checking their existance */

src/cctrl.c:1206

↓ 4 callersFunctioncctrlIce

src/cctrl.c:936

↓ 4 callersFunctioncfgLinkLeaves

Top down through the tree finding blocks which are not pointing to anything */

↓ 4 callersFunctioncliTargetToString

↓ 4 callersFunctioncstringMurmur

src/aostr.c:845

↓ 4 callersFunctionevalIntConstExpr

src/prsutil.c:458

↓ 4 callersFunctionhccJitAddCallFixup

src/jit-common.c:56

↓ 4 callersFunctionhccJitAddLocalBranchFixup

src/jit-common.c:70

↓ 4 callersFunctionhccJitEpilogueLocalNum

src/jit-common.c:37

↓ 4 callersFunctionhccJitFreshLocalNum

src/jit-common.c:45

↓ 4 callersFunctionirCgComputeReferencedBlocks

We should be able to delete this as we already remove unused blocks */

src/ir-regalloc.c:364

↓ 4 callersFunctionirConvertFloatToTargetWidth

Convert a float value to the target float slot's width. The codegen * sizes a float store from the value's byte width, so storing an F64 * value int

↓ 4 callersFunctionirFnHasCalls

True if fn contains an IR_CALL. The x86_64 prologue uses this to * decide whether the leaf-function frame-elision is safe (a call needs * the entry

src/ir-regalloc.c:554

↓ 4 callersFunctionirIsByValAggregate

True for a by-value aggregate (non-intrinsic class/union) - the things * that are copied wholesale rather than held in a register. */

↓ 4 callersFunctionirLowerAssignTarget

↓ 4 callersFunctionirLowerCast

Lower a value of `from_type` (already in `src`) to `to_type`. Returns the * IrValue holding the converted result, or `src` unchanged when no * conve

↓ 4 callersFunctionirPopLoopCtx

↓ 4 callersFunctionirPushLoopCtx

↓ 4 callersFunctionirRegPoolSet

src/ir-regalloc.c:18

↓ 4 callersFunctionirValueKindToString

src/ir-debug.c:72

↓ 4 callersFunctionjitFrameForm

src/aarch64-jit.c:154

↓ 4 callersFunctionjitIsFpRegName

src/aarch64-jit.c:101

↓ 4 callersFunctionlexInit

src/lexer.c:286

↓ 4 callersFunctionlexemeSentinal

src/lexer.c:197

↓ 4 callersFunctionlexerAllocLexeme

↓ 4 callersFunctionlistMergeAppend

Merge l2 to the end of l1 and free l2. * Example * l1 = [1,2,3] * l2 = [4,5,6] * listMerge(l1,l2); * l1 = [1,2,3,4,5,6] (and linked the otherway

↓ 4 callersFunctionmapGetIdx

src/containers.c:803

↓ 4 callersFunctionmemoryRelease

↓ 4 callersFunctionparseBaseDeclSpec

Does not parse pointer types, only the base type */

src/prslib.c:271

↓ 4 callersFunctionparseFunctionArguments

Read function arguments for a function being called */

src/prslib.c:886

↓ 4 callersFunctionparseGetFunctionParams

src/prslib.c:425

↓ 4 callersFunctionparseParams

src/prslib.c:121

↓ 4 callersFunctionsetIterNew

src/containers.c:537

↓ 4 callersFunctiontranspileHighlightInt

src/transpiler.c:367

↓ 4 callersFunctionvecPushInt

src/containers.c:114

↓ 4 callersFunctionx86_64_emit_sse_rm

Emit prefix -> REX -> 0F -> opcode -> memref. `reg_num` is the reg field of * the ModR/M (either dst for loads, or src for stores). */

src/asm/enc_x86_64.c:1973

↓ 4 callersFunctionx86_64_enc_cvt_to_si

src/asm/enc_x86_64.c:2053

↓ 4 callersFunctionx86_64_enc_movabsq_imm_reg

src/asm/enc_x86_64.c:78

↓ 4 callersFunctionx86_64_enc_x87_cmpi

Two-operand FPU compare instructions (FCOMI/FCOMIP/FUCOMI/FUCOMIP). The * left operand must be ST(0) and the right is ST(i). */

src/asm/enc_x86_64.c:1882

↓ 3 callersFunction_aarch64_enc_fcmp

FP compare. Encoding: * 0 0 0 11110 ftype 1 Rm 0010 00 Rn opc2 * * opc2 (5 bits at 4..0): 00000 FCMP reg, 10000 FCMPE reg, *

src/asm/enc_arm64.c:840

↓ 3 callersFunction_aarch64_enc_ldst_unscaled

LDUR/STUR - unscaled signed-imm9 offset. Same encoding as the * pre/post-index family but with op2=00, so the address isn't * writeback-updated. U

src/asm/enc_arm64.c:728

↓ 3 callersFunctiona64JitSrcReg

JIT (machine-code) leaf ops for the shared a64Emit* lowering. The helper * resolves r1 to its live register, or loads it into the scratch. */

src/aarch64-jit.c:772

↓ 3 callersFunctiona64TxtSrcReg

AOT (assembly-text) leaf ops for the shared a64Emit* lowering. The * helper resolves r1 to its live register, or loads it into the scratch. */

src/aarch64.c:873

↓ 3 callersFunctionaarch64DerefLoad

Width-aware load through a register-held address. */

src/aarch64.c:302

↓ 3 callersFunctionaarch64DerefStore

src/aarch64.c:339

↓ 3 callersFunctionaarch64IdxReg

src/aarch64.c:627

↓ 3 callersFunctionaarch64MakeAoStrVec

src/aarch64.c:49

↓ 3 callersFunctionaarch64_enc_adrp

ADRP Xd, #(pages*4096): * op=1 | immlo(2) | 1 0 0 0 0 | immhi(19) | Rd(5) * `pages` is a signed 21-bit count of 4 KiB pages. */

src/asm/enc_arm64.c:1207

↓ 3 callersFunctionaarch64_enc_and_reg

src/asm/enc_arm64.c:1453

↓ 3 callersFunctionaarch64_enc_barrier

DMB/DSB/ISB. Single optional operand: a label (option name) or imm4. * ISB with no operand defaults to SY (CRm=15). */

src/asm/enc_arm64.c:3357

↓ 3 callersFunctionaarch64_enc_bfdot_vec

BF16 instruction encoders (FEAT_BF16, Armv8.6+). Encodings byte-verified * against clang's assembler (armv8.6-a+bf16). They also seem to do what I'd

src/asm/enc_arm64.c:918

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