| 839 | } |
| 840 | |
| 841 | void Gpu::writeCopyCnt(uint32_t mask, uint32_t value) { |
| 842 | // Allow clearing the interrupt bit but not setting it |
| 843 | if ((mask & BIT(8)) && !(value & BIT(8))) |
| 844 | gpuCopy.cnt &= ~BIT(8); |
| 845 | |
| 846 | // Check if a copy should start and schedule the end signal based on type and size |
| 847 | if (!(value & mask & BIT(0)) || !(cfg11GpuCnt & BIT(4))) return; |
| 848 | core.schedule(GPU_END_COPY, (gpuCopy.flags & BIT(3)) ? (gpuCopy.texSize / 4) |
| 849 | : ((gpuCopy.dispDstSize & 0xFFFF) * (gpuCopy.dispDstSize >> 16))); |
| 850 | |
| 851 | // Start the copy now or forward it to the thread if running |
| 852 | if (!thread) return startCopy(gpuCopy); |
| 853 | GpuCopyRegs *regs = new GpuCopyRegs(gpuCopy); |
| 854 | addThreadTask(TASK_COPY, regs); |
| 855 | } |
| 856 | |
| 857 | void Gpu::writeCopyTexSize(uint32_t mask, uint32_t value) { |
| 858 | // Write to the GPU_COPY_TEX_SIZE register |