| 644 | } |
| 645 | |
| 646 | static sljit_s32 emit_op(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 flags, |
| 647 | sljit_s32 dst, sljit_sw dstw, |
| 648 | sljit_s32 src1, sljit_sw src1w, |
| 649 | sljit_s32 src2, sljit_sw src2w) |
| 650 | { |
| 651 | /* arg1 goes to TMP_REG1 or src reg |
| 652 | arg2 goes to TMP_REG2, imm or src reg |
| 653 | TMP_REG3 can be used for caching |
| 654 | result goes to TMP_REG2, so put result can use TMP_REG1 and TMP_REG3. */ |
| 655 | sljit_s32 dst_r = TMP_REG2; |
| 656 | sljit_s32 src1_r; |
| 657 | sljit_sw src2_r = 0; |
| 658 | sljit_s32 sugg_src2_r = TMP_REG2; |
| 659 | |
| 660 | if (!(flags & ALT_KEEP_CACHE)) { |
| 661 | compiler->cache_arg = 0; |
| 662 | compiler->cache_argw = 0; |
| 663 | } |
| 664 | |
| 665 | if (SLJIT_UNLIKELY(dst == SLJIT_UNUSED)) { |
| 666 | if (op >= SLJIT_MOV && op <= SLJIT_MOVU_S32 && !(src2 & SLJIT_MEM)) |
| 667 | return SLJIT_SUCCESS; |
| 668 | } |
| 669 | else if (FAST_IS_REG(dst)) { |
| 670 | dst_r = dst; |
| 671 | flags |= REG_DEST; |
| 672 | if (op >= SLJIT_MOV && op <= SLJIT_MOVU_S32) |
| 673 | sugg_src2_r = dst_r; |
| 674 | } |
| 675 | else if ((dst & SLJIT_MEM) && !getput_arg_fast(compiler, flags | ARG_TEST, TMP_REG1, dst, dstw)) |
| 676 | flags |= SLOW_DEST; |
| 677 | |
| 678 | if (flags & IMM_OP) { |
| 679 | if ((src2 & SLJIT_IMM) && src2w) { |
| 680 | if (src2w <= SIMM_MAX && src2w >= SIMM_MIN) { |
| 681 | flags |= SRC2_IMM; |
| 682 | src2_r = src2w; |
| 683 | } |
| 684 | } |
| 685 | if (!(flags & SRC2_IMM) && (flags & CUMULATIVE_OP) && (src1 & SLJIT_IMM) && src1w) { |
| 686 | if (src1w <= SIMM_MAX && src1w >= SIMM_MIN) { |
| 687 | flags |= SRC2_IMM; |
| 688 | src2_r = src1w; |
| 689 | |
| 690 | /* And swap arguments. */ |
| 691 | src1 = src2; |
| 692 | src1w = src2w; |
| 693 | src2 = SLJIT_IMM; |
| 694 | /* src2w = src2_r unneeded. */ |
| 695 | } |
| 696 | } |
| 697 | } |
| 698 | |
| 699 | /* Source 1. */ |
| 700 | if (FAST_IS_REG(src1)) |
| 701 | src1_r = src1; |
| 702 | else if (src1 & SLJIT_IMM) { |
| 703 | if (src1w) { |
no test coverage detected