| 362 | #endif // ARCH_X86_64 || ARCH_X86_32 |
| 363 | |
| 364 | static void init_cpu_info() |
| 365 | { |
| 366 | if (hb_cpu_info.count != 0) |
| 367 | return; |
| 368 | |
| 369 | hb_cpu_info.name = "Unknown"; |
| 370 | hb_cpu_info.count = init_cpu_count(); |
| 371 | hb_cpu_info.platform = HB_CPU_PLATFORM_UNSPECIFIED; |
| 372 | |
| 373 | #if ARCH_X86_64 || ARCH_X86_32 |
| 374 | if (av_get_cpu_flags() & AV_CPU_FLAG_SSE) |
| 375 | { |
| 376 | int eax, ebx, ecx, edx, family, model; |
| 377 | |
| 378 | cpuid(1, &eax, &ebx, &ecx, &edx); |
| 379 | family = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff); |
| 380 | model = ((eax >> 4) & 0xf) + ((eax >> 12) & 0xf0); |
| 381 | |
| 382 | // Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 4/April 2022 |
| 383 | // Table 2-1. CPUID Signature Values of DisplayFamily_DisplayModel |
| 384 | switch (family) |
| 385 | { |
| 386 | case 0x06: |
| 387 | { |
| 388 | switch (model) |
| 389 | { |
| 390 | case 0x1C: |
| 391 | case 0x26: |
| 392 | case 0x27: |
| 393 | case 0x35: |
| 394 | case 0x36: |
| 395 | hb_cpu_info.platform = HB_CPU_PLATFORM_INTEL_BNL; |
| 396 | break; |
| 397 | case 0x2A: |
| 398 | case 0x2D: |
| 399 | hb_cpu_info.platform = HB_CPU_PLATFORM_INTEL_SNB; |
| 400 | break; |
| 401 | case 0x3A: |
| 402 | case 0x3E: |
| 403 | hb_cpu_info.platform = HB_CPU_PLATFORM_INTEL_IVB; |
| 404 | break; |
| 405 | case 0x37: |
| 406 | case 0x4A: |
| 407 | case 0x4D: |
| 408 | case 0x5A: |
| 409 | case 0x5D: |
| 410 | hb_cpu_info.platform = HB_CPU_PLATFORM_INTEL_SLM; |
| 411 | break; |
| 412 | case 0x3C: |
| 413 | case 0x3F: |
| 414 | case 0x45: |
| 415 | case 0x46: |
| 416 | hb_cpu_info.platform = HB_CPU_PLATFORM_INTEL_HSW; |
| 417 | break; |
| 418 | case 0x3D: |
| 419 | case 0x4F: |
| 420 | case 0x56: |
| 421 | hb_cpu_info.platform = HB_CPU_PLATFORM_INTEL_BDW; |
no test coverage detected