| 1022 | } |
| 1023 | |
| 1024 | static AtomicRMWInst::BinOp getDecodedRMWOperation(unsigned Val) { |
| 1025 | switch (Val) { |
| 1026 | default: return AtomicRMWInst::BAD_BINOP; |
| 1027 | case bitc::RMW_XCHG: return AtomicRMWInst::Xchg; |
| 1028 | case bitc::RMW_ADD: return AtomicRMWInst::Add; |
| 1029 | case bitc::RMW_SUB: return AtomicRMWInst::Sub; |
| 1030 | case bitc::RMW_AND: return AtomicRMWInst::And; |
| 1031 | case bitc::RMW_NAND: return AtomicRMWInst::Nand; |
| 1032 | case bitc::RMW_OR: return AtomicRMWInst::Or; |
| 1033 | case bitc::RMW_XOR: return AtomicRMWInst::Xor; |
| 1034 | case bitc::RMW_MAX: return AtomicRMWInst::Max; |
| 1035 | case bitc::RMW_MIN: return AtomicRMWInst::Min; |
| 1036 | case bitc::RMW_UMAX: return AtomicRMWInst::UMax; |
| 1037 | case bitc::RMW_UMIN: return AtomicRMWInst::UMin; |
| 1038 | } |
| 1039 | } |
| 1040 | |
| 1041 | static AtomicOrdering getDecodedOrdering(unsigned Val) { |
| 1042 | switch (Val) { |